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29F040

4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory

STMicroelectronics 

M29F040

Table 11. DC Characteristics

(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)

Symbol

Parameter

Test Condition

Min

Max

Unit

ILI

Input Leakage Current

0V ≤ VIN ≤ VCC

±1

µA

ILO

Output Leakage Current

0V ≤ VOUT ≤ VCC

±1

µA

ICC1 Supply Current (Read)

E = VIL, G = VIH, f = 6MHz

15

mA

ICC2 Supply Current (Standby) TTL

E = VIH

1

mA

ICC3 Supply Current (Standby) CMOS

E = VCC ± 0.2V

50

µA

ICC4 Supply Current (Program or Erase)

Byte Program,

Block Erase

20

mA

ICC5 Supply Current

Chip Erase in progress

40

mA

VIL

Input Low Voltage

–0.5

0.8

V

VIH

Input High Voltage

2

VCC + 0.5

V

VOL Output Low Voltage

IOL = 10mA

0.45

V

Output High Voltage TTL

IOH = –2.5mA

2.4

V

VOH

Output High Voltage CMOS

IOH = –100µA

VCC –0.4

V

IOH = –2.5mA

0.85 VCC

V

VID

A9 Voltage (Electronic Signature)

11.5

12.5

V

IID

A9 Current (Electronic Signature)

A9 = VID

50

µA

VLKO

Supply Voltage (Erase and

Program lock-out)

3.2

4.2

V

Read Block Protection (RBP) instruction. The

use of Read Electronic Signature (RSIG) command

also allows access to the Block Protection status

verify. After giving the RSIG command, A0 and A6

are set to VIL with A1 at VIH, while A16, A17 and

A18 define the block of the block to be verified. A

read in these conditions will output a 01h if block is

protected and a 00h if block is not protected.

This Read Block Protection is the only valid way to

check the protection status of a block. Neverthe-

less, it must not be used during the Block Protection

phase as a method to verify the block protection.

Please refer to Block Protection paragraph.

Chip Erase (CE) instruction. This instruction uses

six write cycles. The Erase Set-up command 80h

is written to address 5555h on third cycle after the

two coded cycles. The Chip Erase Confirm com-

mand 10h is written at address 5555h on sixth cycle

after another two coded cycles. If the second com-

mand given is not an erase confirm or if the coded

cycles are wrong, the instruction aborts and the

device is reset to Read Array. It is not necessary to

program the array with 00h first as the P/E.C. will

automatically do this before erasing to FFh. Read

operations after the sixth rising edge of W or E

output the status register bits. During the execu-

tion of the erase by the P/E.C. the memory accepts

only the Reset (RST) command. Read of Data

Polling bit DQ7 returns ’0’, then ’1’ on completion.

The Toggle Bit DQ6 toggles during erase operation

and stops when erase is completed. After comple-

tion the Status Register bit DQ5 returns ’1’ if there

has been an Erase Failure because the erasure

has not been verified even after the maximum

number of erase cycles have been executed.

10/31

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