PE9601 Просмотр технического описания (PDF) - Peregrine Semiconductor
Номер в каталоге
Компоненты Описание
производитель
PE9601 Datasheet PDF : 15 Pages
| |||
PE9601
Product Specification
Pin No. Pin Name Interface Mode
Type
Description
30
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
VDD-fc
ALL
(Note 2) VDD for fc.
32
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
33
VDD
ALL
34
Cext
ALL
(Note 1)
Output
Same as pin 1.
Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
35
VDD
ALL
36
CP
ALL
37
NC
ALL
(Note 1)
Output
Same as pin 1.
Charge pump current is sourced for “up” when fc leads fp and sinked for “down” when fc
lags fp.
No connection.
38
VDD-fp
ALL
39
fc
ALL
40
GND
ALL
(Note 2)
Output
VDD for fp
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
Ground.
41
GND
ALL
Ground.
42
fr
43
LD
44
Enh
ALL
ALL
Serial, Parallel
Input
Output,
OD
Input
Reference frequency input. See figure 3.
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Note 1: VDD pins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level.
Note 2: VDD pins 31 and 38 are used to enable test modes and should be left floating.
Figure 3. Looking into the device PIN 42 - fr
PIN 42
125K
2.8pF
Copyright Peregrine Semiconductor Corp. 2001
Page 4 of 15
File No. 70/0025~02C | UTSi CMOS RFIC SOLUTIONS
Share Link: 