24LC320 Просмотр технического описания (PDF) - Microchip Technology
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24LC320 Datasheet PDF : 12 Pages
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25LC320
4.0 PIN DESCRIPTIONS
4.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already in
progress will be completed, regardless of the CS input
signal. If CS is brought high during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is complete. As soon as the device is
deselected, SO goes to the high impedance state,
allowing multiple parts to share the same SPI™ bus. A
low to high transition on CS after a valid write sequence
is what initiates an internal write cycle. After power-up,
a low level on CS is required prior to any sequence
being initiated.
4.2 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data to be written
to the memory. Input is latched on the rising edge of the
serial clock.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two way
communication of data can occur using only one
microcontroller I/O line.
4.3 Serial Output (SO)
The SO pin is used to transfer data out of the 25LC320.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two-way
communication of data can occur using only one
microcontroller I/O line.
4.4 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25LC320. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
4.5 Write Protect (WP)
This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP is low and WPEN is
high, writing to the non-volatile bits in the status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
non-volatile bits in the status register operate normally.
WP going low during a status register write sequence
will disable writing to the status register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.
The WP pin function is blocked when the WPEN bit in
the status register is low. This allows the user to install
the 25LC320 in a system with WP pin grounded and still
be able to write to the status register. The WP pin
functions will be enabled when the WPEN bit is
set high.
4.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25LC320 while in the middle of a serial sequence with-
out having to re-transmit entire sequence over at a later
time. It should be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled low
to pause further serial communication without resetting
the serial sequence. The HOLD pin must be brought
low while SCK is low, otherwise the HOLD function will
not be evoked until the next SCK high to low transition.
The 25LC320 must remain selected during this
sequence. The SI, SCK, and SO pins are in a high
impedance state during the time the part is paused and
transitions on these pins will be ignored. To resume
serial communication, HOLD must be brought high
while the SCK pin is low, otherwise serial communica-
tion will not resume.
DS21158B-page 10
Preliminary
© 1996 Microchip Technology Inc.
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