24AA014H Просмотр технического описания (PDF) - Microchip Technology
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24AA014H Datasheet PDF : 28 Pages
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24AA014H/24LC014H
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
Automotive (E): VCC = +2.5V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
1
FCLK
Clock frequency
—
100
kHz 1.7V ≤ VCC < 1.8V
—
400
1.8V ≤ VCC ≤ 5.5V
—
1000
2.5V ≤ VCC ≤ 5.5V (24LC014H)
2
THIGH
Clock high time
4000
600
500
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
3
TLOW
Clock low time
4700
1300
500
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
4
TR
SDA and SCL rise time (Note 1)
—
1000
ns 1.7V ≤ VCC < 1.8V
—
300
1.8V ≤ VCC ≤ 5.5V
—
300
2.5V ≤ VCC ≤ 5.5V (24LC014H)
5
TF
SDA and SCL fall time (Note 1)
—
1000
ns 1.7V ≤ VCC < 1.8V
—
300
1.8V ≤ VCC ≤ 5.5V
—
300
2.5V ≤ VCC ≤ 5.5V (24LC014H)
6
THD:STA Start condition hold time
4000
600
250
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
7
TSU:STA Start condition setup time
4700
600
250
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
8
THD:DAT Data input hold time
0
—
ns (Note 2)
9
TSU:DAT Data input setup time
250
—
ns 1.7V ≤ VCC < 1.8V
100
—
1.8V ≤ VCC ≤ 5.5V
100
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
10
TSU:STO Stop condition setup time
4000
600
250
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
11
TSU:WP WP setup time
4000
600
600
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
12
THD:WP WP hold time
4700
600
600
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
13
TAA
Output valid from clock (Note 2)
—
3500
ns 1.7V ≤ VCC < 1.8V
—
900
1.8V ≤ VCC ≤ 5.5V
—
400
2.5V ≤ VCC ≤ 5.5V (24LC014H)
14
TBUF
Bus free time: Time the bus must
1300
be free before a new transmission
4700
can start
4700
—
ns 1.7V ≤ VCC < 1.8V
—
1.8V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V (24LC014H)
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns 24AA014H
(Note 1 and Note 3)
17
TWC
Write cycle time (byte or page)
—
5
ms —
18
—
Endurance
1M
—
cycles 25°C, VCC = 5.5V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
© 2008 Microchip Technology Inc.
Preliminary
DS22077B-page 3
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