LTC1709EG Просмотр технического описания (PDF) - Linear Technology

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LTC1709EG

2-Phase, 5-Bit Adjustable, High Efficiency, Synchronous Step-Down Switching Regulator

Linear Technology 

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OPERATIO (Refer to Functional Diagram)

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both VOUT+ and VOUT– benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. The AMPMD pin

allows selection of internal, precision feedback resistors

for high common mode rejection differencing applica-

tions, or direct access to the actual amplifier inputs

without these internal feedback resistors for other applica-

tions. The AMPMD pin is grounded to connect the internal

precision resistors in a unity-gain differencing application,

or tied to the INTVCC pin to bypass the internal resistors

and make the amplifier inputs directly available. The

amplifier is a unity-gain stable, 2MHz gain-bandwidth,

>120dB open-loop gain design. The amplifier has an

output slew rate of 5V/µs and is capable of driving capaci-

tive loads with an output RMS current typically up to

35mA. The amplifier is not capable of sinking current and

therefore must be resistively loaded to do so.

LTC1709

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the controllers

have been given time, as determined by the capacitor on

the RUN/SS pin, to charge up the output capacitors and

provide full-load current, the RUN/SS capacitor is then

used as a short-circuit timeout circuit. If the output voltage

falls to less than 70% of its nominal output voltage the

RUN/SS capacitor begins discharging assuming that the

output is in a severe overcurrent and/or short-circuit

condition. If the condition lasts for a long enough period

as determined by the size of the RUN/SS capacitor, the

controller will be shut down until the RUN/SS pin voltage

is recycled. This built-in latchoff can be overidden by

providing a current >5µA at a compliance of 5V to the

RUN/SS pin. This current shortens the soft-start period

but also prevents net discharge of the RUN/SS capacitor

during a severe overcurrent and/or short-circuit condi-

tion. Foldback current limiting is activated when the output

voltage falls below 70% of its nominal level whether or not

the short-circuit latchoff circuit is enabled.

APPLICATIO S I FOR ATIO

The basic LTC1709 application circuit is shown in Figure␣ 1

on the first page. External component selection begins

with the selection of the inductor(s) based on ripple

current requirements and continues with the RSENSE1, 2

resistor selection using the calculated peak inductor cur-

rent and/or maximum current limit. Next, the power

MOSFETs and D1 and D2 are selected. The operating

frequency and the inductor are chosen based mainly on

the amount of ripple current. Finally, CIN is selected for its

ability to handle the input ripple current (that PolyPhaseTM

operation minimizes) and COUT is chosen with low enough

ESR to meet the output ripple voltage and load step

specifications (also minimized with PolyPhase). Current

mode architecture provides inherent current sharing be-

tween output stages. The circuit shown in Figure␣ 1 can be

configured for operation up to an input voltage of 28V

(limited by the external MOSFETs).

RSENSE Selection For Output Current

RSENSE1, 2 are chosen based on the required peak output

current. The LTC1709 current comparator has a maxi-

mum threshold of 75mV/RSENSE and an input common

mode range of SGND to 1.1( INTVCC). The current com-

parator threshold sets the peak inductor current, yielding

a maximum average output current IMAX equal to the peak

value less half the peak-to-peak ripple current, ∆IL.

Allowing a margin for variations in the LTC1709 and

external component values yields:

RSENSE = 2(50mV/IMAX)

Operating Frequency

The LTC1709 uses a constant frequency, phase-lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

PolyPhase is a registered trademark of Linear Technology Corporation.

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