PM7325-TC Просмотр технического описания (PDF) - PMC-Sierra
Номер в каталоге
Компоненты Описание
производитель
PM7325-TC Datasheet PDF : 432 Pages
| |||
S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Public Revision History
Issue
No.
1
Draft 1
Draft 2
Draft 3
Draft 4
Issue Date
May 1999
June 1999
Aug 1999
Aug 1999
Draft 5 Sep 1999
Details of Change
Initial draft.
Added detailed functional description, register listing,functional timing.
Aligns with newest 2-chip Embedded-DRAM Solution.
Corrected and updated information on UL3 and POS interfaces, per-PHY
counting, packet bypass, routing of APS cells. Added Operations Section.
TAT and PHYTAT increased to 34 bits. Backwards VCRA and PHYID moved
to Linkage Row to help make room. Policing Reserved moved to Row 1 and
Parity to Row 0, also to make room. Frame counts added to per-PHY policing.
Core Logic Voltage changed to 1.8V. I/O voltage clarified to be 3.3V. Parity
added on Address of SRAM as well as data. Pin and block diagrams
corrected. PHYID added to Secondary Key. Field B expanded from 11 to 12
bits. Unused bits in Search Table and Linkage Row redistributed to easily
accommodate future expansion. Drop_VC does not permit the generation any
cells on that connection, whether to OCIF or BCIF. Operation of MCR in GFR
policing clarified to explicitly state that MCR operations are performed on
frame boundaries only. AUTO_RDI becomes a per-VC bit. DRAM bank
number changed to the 2 LSBs of the VCRA rather than the 2 MSBs. Per-
PHY counts updated to include counts of EFCI and Timed-Out cells. SRAM,
DRAM, per-PHY policing, and PM microprocessor accesses adjusted to
access entire records at once, and to have per-field write and Clear-On-Read
masks. Basic description of DRAM and SRAM bandwidth allocation added.
Gen_halfsecclk bit moved to CP. Slow Background Processing Interrupt
added. Capability to switch Input BCIF to Slave mode for use with testers
added. Placement of interrupts in Utopia/POS and SDQ blocks changed.
Burst length set to a maximum of 256 bytes. Buffer Available thresholds set to
a max of 511 bytes. Package changed from 432 TBGA to 576 TBGA to add
power/ground balls. Documented separate 1.5V supply for the DRAM. Lower
bound of temperature range changed to 0 degrees C. Address map adjusted
for easier decode. Added APS cell routing back in.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
4
Document ID: PMC-1990553, Issue 4
Share Link: 