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SST31LF021E

2 Mbit Flash + 1 Mbit SRAM ComboMemory

Silicon Storage Technology 

2 Mbit Flash + 1 Mbit SRAM ComboMemory

SST31LF021 / SST31LF021E

EOL Data Sheet

Flash Byte-Program Operation

The flash memory bank of the SST31LF021/021E devices

are programmed on a byte-by-byte basis. Before the Pro-

gram operations, the memory must be erased first. The

Program operation consists of three steps. The first step is

the three-byte load sequence for Software Data Protection.

The second step is to load byte address and byte data.

During the Byte-Program operation, the addresses are

latched on the falling edge of either BEF# or WE#, which-

ever occurs last. The data is latched on the rising edge of

either BEF# or WE#, whichever occurs first. The third step

is the internal Program operation which is initiated after the

rising edge of the fourth WE# or BEF#, whichever occurs

first. The Program operation, once initiated, will be com-

pleted, within 20 µs. See Figures 5 and 6 for WE# and

BEF# controlled Program operation timing diagrams and

Figure 16 for flowcharts. During the Program operation, the

only valid Flash Read operations are Data# Polling and

Toggle Bit. During the internal Program operation, the host

is free to perform additional tasks. Any SDP commands

loaded during the internal Program operation will be

ignored.

Flash Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

flash memory bank on a sector-by-sector basis. The sector

architecture is based on uniform sector size of 4 KByte.

The Sector-Erase operation is initiated by executing a six-

byte command load sequence for Software Data Protec-

tion with Sector-Erase command (30H) and sector address

(SA) in the last bus cycle. The address lines A17-A12 will be

used to determine the sector address. The sector address

is latched on the falling edge of the sixth WE# pulse, while

the command (30H) is latched on the rising edge of the

sixth WE# pulse. The internal Erase operation begins after

the sixth WE# pulse. The End-of-Erase can be determined

using either Data# Polling or Toggle Bit methods. See Fig-

ure 9 for timing waveforms. Any SDP commands loaded

during the Sector-Erase operation will be ignored.

Flash Bank-Erase Operation

The SST31LF021/021E flash memory bank provides a

Bank-Erase operation, which allows the user to erase the

entire flash memory bank array to the ‘1’s state. This is use-

ful when the entire bank must be quickly erased. The Bank-

Erase operation is initiated by executing a six-byte Software

Data Protection command sequence with Bank-Erase com-

mand (10H) with address 5555H in the last byte sequence.

The internal Erase operation begins with the rising edge of

the sixth WE# or BEF# pulse, whichever occurs first. During

the internal Erase operation, the only valid Flash Read oper-

ations are Toggle Bit and Data# Polling. See Table 4 for the

command sequence, Figure 10 for timing diagram, and Fig-

ure 19 for the flowchart. Any SDP commands loaded during

the Bank-Erase operation will be ignored.

Flash Write Operation Status Detection

The SST31LF021/021E flash memory bank provides two

software means to detect the completion of a flash memory

bank Write (Program or Erase) cycle, in order to optimize

the system Write cycle time. The software detection

includes two status bits: Data# Polling (DQ7) and Toggle Bit

(DQ6). The End-of-Write detection mode is enabled after

the rising edge of WE#, which initiates the internal Program

or Erase operation. The actual completion of the nonvola-

tile write is asynchronous with the system; therefore, either

a Data# Polling or Toggle Bit Read may be simultaneous

with the completion of the Write cycle. If this occurs, the

system may possibly get an erroneous result, i.e., valid

data may appear to conflict with either DQ7 or DQ6. In

order to prevent spurious rejection, if an erroneous result

occurs, the software routine should include a loop to read

the accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

©2007 Silicon Storage Technology, Inc.

3

S71137-06-EOL

05/07

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