UPD2845GR Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD2845GR

1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM

NEC => Renesas Technology 

PPD2845GR

INPUT SIGNAL DIVIDER

INPUT SIGNAL DIVIDER obtain the frequency: fp input to phase comparator. This circuit divides input frequency:

fin to obtain fp. This block consists of prescaler, 5 bit swallow counter, 13 bit main counter and divide-ratio control

circuit.

Setting numbers

• Main counter

• Swallow counter

• Prescaler

M = 32 to 8 191

S = 0 to 31

P = 32, P+1 = 33

Total divide ratio

NT = S(P+1) + P(MðS) = PM+S = 32 M+S (M t S)

?NT = 1 024 to 262 143

Relation between fp and fin

fp = fin/(32 M+S)

(ex)

At fp = 5 kHz

fin = 70 MHz

NT = 70 M/5 k = 14 000

Therefore 14 000 32 = 437 • • • 16

n

n

M

S

Reference Counter

Reference Counter obtain the frequency: fr input to phase comparater. This circuit divides the reference

oscillating frequency: fX’tal of X’tal or TCXO to obtain fr. This block consists of 13 bit programmable reference counter

and prescaler of divide-by-2.

Setting number

• 13 bit programmable reference counter R = 2 to 8 191

Total reference counter block divide ratio

RT = 2 u R

?RT = 4 to 16 382

Relation between fr and fX’tal

fr = (fX’tal/2)/R

(ex)

fr = 5 kHz

fX’tal = 12.8 MHz

R = (12.8 MHz/2)/5 kHz = 1 280

9

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