UPD2845GR Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD2845GR Datasheet PDF : 16 Pages
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PPD2845GR
NT = 32M + S
= 32 u {(D1 u 212) + (D2 u 211) + (D3 u 210) + (D4 u 29) + (D5 u 28) + (D6 u 27) + (D7 u 26) + (D8 u 25) + (D9 u 24) +
(D10 u 23) + (D11 u 22) + (D12 u 21) + (D13 u 20)} + {(D14 u 24) + (D15 u 23) + (D16 u 22) + (D17 u 21) + (D18 u
20)}
?NT = (D1 u 217) + (D2 u 216) + (D3 u 215) + (D4 u 214) + (D5 u 213) + (D6 u 212) + (D7 u 211) + (D8 u 210) + (D9 u 29) +
(D10 u 28) + (D11 u 27) + (D12 u 26) + (D13 u 25) + (D14 u 24) + (D15 u 23) + (D16 u 22) + (D17 u 21) + (D18 u 20)
Thus, total divide ratio of input signal divider ‘NT’ can be transferred to binary-code in order to setting data ‘D1 to
D18’ input. (D1 should be top digit and D18 should be bottom digit.)
• Charge pump output selection data
D22 D21
0
0
0
1
1
0
1
1
EO Pin
(To use internal
charge pump)
Hi- Impedance
Hi-Impedance
OUTPUT
OUTPUT
EOP, EO Pin
(To use external
charge pump)
OFF
OUTPUT
OFF
OUTPUT
“0” = Low, “1” = High
(3) Setting for reference counter
A D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
A 20 21 22 23 24 25 26 27 28 29 210 211 212 0
1
A=0
reference counter : R
(13 bits 2 to 8 191)
TEST BIT
(FR pin)
no assigned
CAUTION D1 to D7 are not assigned for setting but CLK signals must be input because of the bit
construction.
RT = 2 u R
?RT = 2 u {(D10 u 212) + (D11 u 211) + (D12 u 210) + (D13 u 29) + (D14 u 28) + (D15 u 27) + (D16 u 26) + (D17 u 25) +
(D18 u 24) + (D19 u 23) + (D20 u 22) + (D21 u 21) + (D22 u 20)}
*TEST BIT: for IC tester (FR pin) use or not use (PLL operation).
for normally PLL operation, input D9 = 0, D8 = 1 (FR pin = output L).
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