CY7C1382CV25-200AI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1382CV25-200AI Datasheet PDF : 33 Pages
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PRELIMINARY
Write Cycle Descriptions[1, 5, 6]
Function (1380CV25)
Read
Read
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
GW
BWE
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
X
BWd
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
CY7C1380CV25
CY7C1382CV25
BWc
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
BWb
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
BWa
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
Function (1382CV25)
Read
Read
Write Byte 0 – DQ[7:0] and DP0
Write Byte 1 – DQ[15:8] and DP1
Write All Bytes
Write All Bytes
GW
BWE
BWb
BWa
1
1
X
X
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
X
X
X
Notes:
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a
“don't care” for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or
when the device is deselected, and DQ = data when OE is active.
Document #: 38-05240 Rev. *A
Page 11 of 33
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