CY7C1382CV25-200BGC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1382CV25-200BGC Datasheet PDF : 33 Pages
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PRELIMINARY
CY7C1380CV25
CY7C1382CV25
Cycle Descriptions[1, 2, 3, 4]
Next Cycle Add. Used ZZ
Unselected
None
0
CE3 CE2 CE1 ADSP ADSC ADV OE
X
X
1
X
0
X
X
Unselected
None
0
1
X
0
0
X
X
X
Unselected
None
0
X
0
0
0
X
X
X
Unselected
None
0
1
X
0
1
0
X
X
Unselected
None
0
X
0
0
1
0
X
X
Begin Read
External
0
0
1
0
0
X
X
X
Begin Read
External
0
0
1
0
1
0
X
X
Continue Read Next
0
X
X
X
1
1
0
1
Continue Read Next
0
X
X
X
1
1
0
0
Continue Read Next
0
X
X
1
X
1
0
1
Continue Read Next
0
X
X
1
X
1
0
0
Suspend Read Current
0
X
X
X
1
1
1
1
Suspend Read Current
0
X
X
X
1
1
1
0
Suspend Read Current
0
X
X
1
X
1
1
1
Suspend Read Current
0
X
X
1
X
1
1
0
Begin Write
Current
0
X
X
X
1
1
1
X
Begin Write
Current
0
X
X
1
X
1
1
X
Begin Write
External
0
0
1
0
1
0
X
X
Continue Write Next
0
X
X
X
1
1
0
X
Continue Write Next
0
X
X
1
X
1
0
X
Suspend Write Current
0
X
X
X
1
1
1
X
Suspend Write Current
0
X
X
1
X
1
1
X
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2 and CE3 are available only in the TQFP package. The BGA package has a single chip select, CE1.
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Document #: 38-05240 Rev. *A
Page 10 of 33
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