CY7C1382CV25-167BGC(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1382CV25-167BGC Datasheet PDF : 33 Pages
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CY7C1382CV25–Pin Definitions (continued)
Name
GW
TQFP
88
BGA
H4
fBGA
B7
BWE
87
M4
A7
CLK
89
K4
B6
CE1
98
E4
A3
CE2[2]
97
-
B3
CE3 [2]
92
-
A6
OE
86
F4
B8
ADV
83
G4
A9
ADSP
84
A4
B9
ADSC
85
P4
A8
CY7C1380CV25
CY7C1382CV25
I/O
Description
Input- Global Write Enable Input, active LOW.
Synchronous When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on BWX
and BWE).
Input- Byte Write Enable Input, active LOW.
Synchronous Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
Input- Chip Enable 1 Input, active LOW. Sampled
Synchronous on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the
device. ADSP is ignored if CE1 is HIGH.
Input- Chip Enable 2 Input, active HIGH. Sampled
Synchronous on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the
device.
Input- Chip Enable 3 Input, active LOW. Sampled
Synchronous on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the
device. Not available for AJ package
version.Not connected for BGA. Where refer-
enced, CE3 is assumed active throughout this
document for BGA.
Input- Output Enable, asynchronous input, active
Asynchronou LOW. Controls the direction of the I/O pins.
s
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
Input- Advance Input signal, sampled on the
Synchronous rising edge of CLK, active LOW. When
asserted, it automatically increments the
address in a burst cycle.
Input- Address Strobe from Processor, sampled
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
Input- Address Strobe from Controller, sampled
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Document #: 38-05240 Rev. *C
Page 9 of 33
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