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CY7C1380CV25-200BZC(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C1380CV25-200BZC
(Rev.:2004)
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Cypress Semiconductor
CY7C1380CV25-200BZC Datasheet PDF : 33 Pages
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CY7C1380CV25
CY7C1382CV25
1
Logic Block Diagram – CY7C1380CV25 (512K x 36)
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
D
BW
C
BW
B
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ADDRESS
REGISTER
2
A
[1:0]
Q1
BURST
COUNTER
CLR
AND
Q0
LOGIC
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
ZZ
SLEEP
CONTROL
2
Logic Block Diagram – CY7C1382CV25 (1M x 18)
OUTPUT
BUFFERS
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
INPUT
REGISTERS
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
B
BW
A
BWE
GW
CE
1
CE2
CE3
OE
ADDRESS
REGISTER
2
A[1:0]
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
DQ
B,
DQP
B
WRITE REGISTER
DQ
A,
DQP
A
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ
B,
DQP
B
WRITE DRIVER
DQ
A,
DQP
A
WRITE DRIVER
MEMORY
ARRAY
SENSE
OUTPUT
AMPS
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
A
DQP
B
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
3
Document #: 38-05240 Rev. *C
Page 2 of 33
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