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RLP1N06CLE Просмотр технического описания (PDF) - Intersil

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RLP1N06CLE Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
RLP1N06CLE
device, like most Power MOSFET devices today, is limited to
175oC. The maximum voltage allowable can, therefore be
expressed as:
VDS = I-(-L-1---I7--M--5---o-×---C-(---R--–--θ--T-J---A-C---M--+---B--R--I--Eθ---C-N----AT---)-)
(EQ. 1)
Duty Cycle Operation of the RLP1N06CLE
In many applications either the drain to source voltage or the
gate drive is not available 100% of the time. The copper
header on which the RLP1N06CLE is mounted has a very
large thermal storage capability, so for pulse widths of less
than 100 milliseconds, the temperature of the header can be
considered a constant case temperature calculated simply as:
TC = (VDS × ID × D × RθCA) + TAMBIENT
(EQ. 2)
Generally the heat storage capability of the silicon chip in a
power transistor is ignored for duty cycle calculations.
Making this assumption, limiting junction temperature to
175oC and using the TC calculated above, the expression for
maximum VDS under duty cycle operation is:
VDS = I--L----I--M--1---7-×---5-D----–--×--T---R-C----θ---J---C--
(EQ. 3)
These values are plotted as Figures 12 thru 16.
Limited Time Operations of the RLP1N06CLE
Protection for a limited period of time is sufficient for many
applications. As stated above the heat storage in the silicon
chip can usually be ignored for computations of over 10
milliseconds and the thermal equivalent circuit reduces to a
simple enough circuit to allow easy computation on the
limiting conditions. The variation in limiting current with
temperature complicates the calculation of junction
temperature, but a simple straight line approximation of the
variation is accurate enough to allow meaningful
computations. The curves shown as figures 17 thru 21 give
an accurate indication of how long the specified voltage can
be applied to the device in the current limiting mode without
exceeding the maximum specified 175oC junction
temperature. In practice this tells you how long you have to
alleviate the condition causing the current limiting to occur.
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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