ATMEGA32U4RC-MU(2016) Просмотр технического описания (PDF) - Atmel Corporation

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ATMEGA32U4RC-MU
(Rev.:2016)

8-bit Microcontroller with 16/32K bytes of ISP Flash and USB Controller

Atmel Corporation 

4. AVR CPU Core

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure

correct program execution. The CPU must therefore be able to access memories, perform calculations, control

peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Instruction

Register

Instruction

Decoder

Control Lines

Program

Counter

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

Data

SRAM

EEPROM

I/O Module1

I/O Module 2

I/O Module n

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate

memories and buses for program and data. Instructions in the program memory are executed with a single level

pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program memory is In-System

Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle

access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two

ATmega16U4/32U4 [DATASHEET]

9

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

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