MT6582 Просмотр технического описания (PDF) - MediaTek Inc
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MT6582 Datasheet PDF : 51 Pages
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MT6582
HSPA+ Smartphone Application Processor
Technical Brief
Confidential A
Processor DVFS+SRAM voltage :
1.05V~1.26V (Typ. 1.15V ; sleep mode
0.85V)
I/O voltage: 1.8V/2.8V/3.3V
Memory: 1.2V
NAND: 1.8V/2.8V
LCM interface: 1.8V
Clock source: 26-MHz, 32.768-kHz
Package
Type: FCCSP
10.6mm x 11mm
Height: 1.0mm maximum
Ball count: 475 balls
Ball pitch: 0.4mm
1.2 MODEM Features
3G UMTS FDD supported features (with
MT6166)
3G modem supports most main features
in 3GPP Release 7 and Release 8
CPC (DTX in CELL_DCH, UL DRX DL
DRX), HS-SCCH-less, HS-DSCH
Dual cell operation
MAC-ehs
Two DRX (receiver diversity) schemes
in URA_PCH and CELL_PCH
Uplink Cat. 6, throughput up to 5.7Mbps
Downlink Cat. 14, throughput up to
21Mbps
Fast dormancy
ETWS
Network selection enhancements
Programmable radio Rx filter with
adaptive gain control
Dedicated Rx filter for FB acquisition
Baseband Parallel Interface (BPI) with
programmable driving strength (shared
by 2G & 3G modem)
Supports multi-band
GSM modem and voice CODEC
Dial tone generation
Noise reduction
Echo suppression
Advanced sidetone oscillation reduction
Digital sidetone generator with
programmable gain
Two programmable acoustic
compensation filters
GSM quad vocoders for adaptive
multirate (AMR), enhanced full rate
(EFR), full rate (FR) and half rate (HR)
GSM channel coding, equalization and
A5/1, A5/2 and A5/3 ciphering
GPRS GEA1, GEA2 and GEA3
ciphering
Programmable GSM/GPRS/EDGE
modem
Packet switched data with
CS1/CS2/CS3/CS4 coding schemes
GSM circuit switch data
GPRS/EDGE Class 12
Supports SAIC (single antenna
interference cancellation) technology
Supports VAMOS (Voice services over
Adaptive Multi-user channels on One
Slot) technology in R9 spec
Radio interface and baseband front-end
High dynamic range delta-sigma ADC
converts the downlink analog I and Q
signals to digital baseband
10-bit D/A converter for Automatic
Power Control (APC)
1.3 Multimedia Features
Display
Supports portrait panel resolution up to
HD (1280x720)
MIPI DSI interface (4 data lanes)
MediaTek Confidential
© 2013 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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