BCM2835 Просмотр технического описания (PDF) - Broadcom Corporation

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BCM2835

BCM2835 ARM Peripherals

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0x7E21 50C8 AUX_SPI1_STAT_REG SPI 2 Status

32

0x7E21 50D0 AUX_SPI1_IO_REG

SPI 2 Data

32

0x7E21 50D4 AUX_SPI1_PEEK_REG SPI 2 Peek

16

2.1.1 AUX registers

There are two Auxiliary registers which control all three devices. One is the interrupt status

register, the second is the Auxiliary enable register. The Auxiliary IRQ status register can

help to hierarchically determine the source of an interrupt.

AUXIRQ Register (0x7E21 5000)

SYNOPSIS The AUXIRQ register is used to check any pending interrupts which may be asserted by

the three Auxiliary sub blocks.

Bit(s) Field Name

31:3

2

SPI 2 IRQ

1

SPI 1 IRQ

0

Mini UART

IRQ

Description

Reserved, write zero, read as don’t care

If set the SPI 2 module has an interrupt pending.

If set the SPI1 module has an interrupt pending.

If set the mini UART has an interrupt pending.

Type

R

R

R

Reset

0

0

0

AUXENB Register (0x7E21 5004)

SYNOPSIS The AUXENB register is used to enable the three modules; UART, SPI1, SPI2.

Bit(s)

31:3

2

1

0

Field Name

SPI2 enable

SPI 1 enable

Mini UART

enable

Description

Reserved, write zero, read as don’t care

If set the SPI 2 module is enabled.

If clear the SPI 2 module is disabled. That also

disables any SPI 2 module register access

If set the SPI 1 module is enabled.

If clear the SPI 1 module is disabled. That also

disables any SPI 1 module register access

If set the mini UART is enabled. The UART will

immediately start receiving data, especially if the

UART1_RX line is low.

If clear the mini UART is disabled. That also disables

any mini UART register access

Type

R/W

R/W

R/W

Reset

0

0

0

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW

© 2012 Broadcom Corporation. All rights reserved

Page 9

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