ST7066 Просмотр технического описания (PDF) - Unspecified

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ST7066

Dot Matrix LCD Controller/Driver

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ST7066

Character Generator ROM (CGROM)

The character generator ROM generates 5 x 8 dot or 5 x 11 dot character patterns from 8-bit character codes. It can

generate 208 5 x 8 dot character patterns and 32 5 x 11 dot character patterns. User-defined character patterns are

also available by mask-programmed ROM.

Character Generator RAM (CGRAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character

patterns can be written, and for 5 x 11 dots, four character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character

patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used

for display can be used as general data RAM.

Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as

DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU

access are generated separately to avoid interfering with each other. Therefore, when writing data to

DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than

the display area.

LCD Driver Circuit

LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is

transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is selected

by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. In case of

1-line display mode, COM1 ~ COM8 have 1/8 duty or COM1 ~ COM11 have 1/11duty , and in 2-line mode, COM1 ~

COM16 have 1/16 duty ratio.

Cursor/Blink Control Circuit

It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the

display data RAM address set in the address counter.

V1.2

9

2000/6/13

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