LPC1110FD20 Просмотр технического описания (PDF) - NXP Semiconductors.

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LPC1110FD20

32-bit ARM Cortex-M0 microcontroller; up to 64 kB flash and 8 kB SRAM / LQFP48 package, HVQFN33 package, and TFBGA48 package

NXP Semiconductors. 

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

Table 3. LPC1113/14 pin description table (LQFP48 package) …continued

Symbol

Pin Type Description

XTALIN

6[5]

I

Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT

7[5]

O

Output from the oscillator amplifier.

VSS

5; 41 I

Ground.

[1] See Figure 27 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode.

[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 26).

[3] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 26).

[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

Table 4. LPC1114 pin description table (PLCC44 package)

Symbol

Pin Type Description

PIO0_0 to PIO0_11

I/O

Port 0 — Port 0 is a 12-bit I/O port with individual direction and function

controls for each bit. The operation of port 0 pins depends on the function

selected through the IOCONFIG register block.

RESET/PIO0_0

7[1]

I

RESET — External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default states, and

processor execution to begin at address 0.

I/O

PIO0_0 — General purpose digital input/output pin.

PIO0_1/CLKOUT/

CT32B0_MAT2

8[2]

I/O

PIO0_1 — General purpose digital input/output pin. A LOW level on this pin

during reset starts the ISP command handler.

O

CLKOUT — Clockout pin.

O

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0

14[2] I/O

O

PIO0_2 — General purpose digital input/output pin.

SSEL0 — Slave Select for SPI0.

I

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3

18[2] I/O

PIO0_3 — General purpose digital input/output pin.

PIO0_4/SCL

19[3] I/O

PIO0_4 — General purpose digital input/output pin (open-drain).

I/O

SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C

Fast-mode Plus is selected in the I/O configuration register.

PIO0_5/SDA

20[3] I/O

PIO0_5 — General purpose digital input/output pin (open-drain).

I/O

SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C

Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/SCK0

26[2] I/O

PIO0_6 — General purpose digital input/output pin.

I/O

SCK0 — Serial clock for SPI0.

PIO0_7/CTS

27[2] I/O

PIO0_7 — General purpose digital input/output pin (high-current output

driver).

I

CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0

31[2] I/O

I/O

PIO0_8 — General purpose digital input/output pin.

MISO0 — Master In Slave Out for SPI0.

O

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

LPC1111_12_13_14_1

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 01 — 16 April 2010

© NXP B.V. 2010. All rights reserved.

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