MFRC52202HN1 Просмотр технического описания (PDF) - NXP Semiconductors.

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MFRC52202HN1

Standard performance MIFARE and NTAG frontend

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

8.1.2 Serial Peripheral Interface

A serial peripheral interface (SPI compatible) is supported to enable high-speed

communication to the host. The interface can handle data speeds up to 10 Mbit/s. When

communicating with a host, the MFRC522 acts as a slave, receiving data from the

external host for register settings, sending and receiving data relevant for RF interface

communication.

An interface compatible with SPI enables high-speed serial communication between the

MFRC522 and a microcontroller. The implemented interface is in accordance with the SPI

standard.

The timing specification is given in Section 14.1 on page 78.

SCK

MOSI

MISO

NSS

MFRC522

SCK

MOSI

MISO

NSS

001aak586

Fig 7. SPI connection to host

The MFRC522 acts as a slave during SPI communication. The SPI clock signal SCK must

be generated by the master. Data communication from the master to the slave uses the

MOSI line. The MISO line is used to send data from the MFRC522 to the master.

Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI

and MISO lines must be stable on the rising edge of the clock and can be changed on the

falling edge. Data is provided by the MFRC522 on the falling clock edge and is stable

during the rising clock edge.

8.1.2.1 SPI read data

Reading data using SPI requires the byte order shown in Table 6 to be used. It is possible

to read out up to n-data bytes.

The first byte sent defines both the mode and the address.

Table 6. MOSI and MISO byte order

Line

Byte 0

Byte 1

Byte 2

To

MOSI

address 0 address 1 address 2 ...

MISO

X[1]

data 0

data 1

...

[1] X = Do not care.

Remark: The MSB must be sent first.

Byte n

address n

data n  1

Byte n + 1

00

data n

MFRC522

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.9 — 27 April 2016

112139

© NXP Semiconductors N.V. 2016. All rights reserved.

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