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8P34S1208

1:8 LVDS Output 1.8V Fanout Buffer

Integrated Device Technology 

IDT8P34S1208I Data Sheet

1:8 LVDS OUTPUT 1.8V FANOUT BUFFER

Pin Description and Pin Characteristic Tables

Table 1. Pin DescriptionsNote 1.

Number

Name

Type

Description

1, 14

GND

Power

Power supply pin.

2, 3

Q7, nQ7

Output

Differential output pair 7. LVDS interface levels.

4

SEL

Input

Pulldown Reference select control pin. See Table 3 for function. LVCMOS/LVTTL

interface levels.

5

CLK1

Input

Pulldown Non-inverting differential clock/data input 1.

6

nCLK1

Input

Pullup/

Pulldown Inverting differential clock/data input 1. VDD/2 default when left floating.

7

VREF1

Output

Bias voltage reference. Provides an input bias voltage for the CLK1, nCLK1

input pair in AC-coupled applications. Refer to Figures 2B and 2C for

applicable AC-coupled input interfaces.

8, 15, 28

9

10

11

VDD

CLK0

nCLK0

VREF0

Power

Input

Input

Output

Pulldown

Pullup/

Pulldown

Power supply pin.

Non-inverting differential clock/data input 0.

Inverting differential clock/data input 0. VDD/2 default when left floating.

Bias voltage reference. Provides an input bias voltage for the CLK0, nCLK0

input pair in AC-coupled applications. Refer to Figures 2B and 2C for

applicable AC-coupled input interfaces.

12, 13

Q0, nQ0

Output

Differential output pair 0. LVDS interface levels.

16, 17

Q1, nQ1

Output

Differential output pair 1. LVDS interface levels.

18, 19

Q2, nQ2

Output

Differential output pair 2. LVDS interface levels.

20, 21

Q3, nQ3

Output

Differential output pair 3. LVDS interface levels.

22, 23

Q4, nQ4

Output

Differential output pair 4. LVDS interface levels.

24, 25

Q5, nQ5

Output

Differential output pair 5. LVDS interface levels.

26, 27

Q6, nQ6

Output

Differential output pair 6. LVDS interface levels.

1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

CIN

RPULLDOWN

RPULLUP

Input Capacitance

Input Pulldown Resistor

Input Pullup Resistor

Test Conditions

Minimum

Typical

2

51

51

Maximum

Units

pF

k

k

Table 3. SEL Input Function TableNote 1.

Input

SEL

Operation

0

CLK0, nCLK0 is the selected differential clock input.

1

CLK1, nCLK1 is the selected differential clock input.

1. SEL is an asynchronous control.

IDT8P34S1208NBGI REVISION A JANUARY 22, 2014

2

©2014 Integrated Device Technology, Inc.

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