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8P34S1208

1:8 LVDS Output 1.8V Fanout Buffer

Integrated Device Technology 

IDT8P34S1208I Data Sheet

1:8 LVDS OUTPUT 1.8V FANOUT BUFFER

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V1= VDD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V1in the center of the input voltage swing. For

example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2

value should be adjusted to set V1 at 1.25V. The values below are for

when both the single ended swing and VDD are at the same voltage.

This configuration requires that the sum of the output impedance of

the driver (Ro) and the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the input will

attenuate the signal in half. This can be done in one of two ways.

First, R3 and R4 in parallel should equal the transmission line

impedance. For most 50 applications, R3 and R4 can be 100. The

values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however VIL cannot be less

than -0.3V and VIH cannot be more than VDD + 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

Recommendations for Unused Input and Output Pins

Inputs:

CLK/nCLK Inputs

For applications not requiring the use of a differential input, both the

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

Outputs:

LVDS Outputs

Unused LVDS outputs must either have a 100 differential

termination or have a 100 pullup resistor to VDD in order to ensure

proper device operation.

IDT8P34S1208NBGI REVISION A JANUARY 22, 2014

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©2014 Integrated Device Technology, Inc.

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