RTL8211EG-VB-CG Просмотр технического описания (PDF) - Realtek Semiconductor
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RTL8211EG-VB-CG Datasheet PDF : 79 Pages
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RTL8211E/RTL8211EG
Datasheet
List of Figures
FIGURE 1. APPLICATION DIAGRAM (RTL8211E-VB)....................................................................................................................3
FIGURE 2. APPLICATION DIAGRAM (RTL8211EG-VB).................................................................................................................4
FIGURE 3. APPLICATION DIAGRAM (RTL8211EG-VL).................................................................................................................4
FIGURE 4. BLOCK DIAGRAM..........................................................................................................................................................5
FIGURE 5. RTL8211E-VB/RTL8211E-VL PIN ASSIGNMENTS (48-PIN QFN) ..............................................................................6
FIGURE 6. RTL8211EG-VB PIN ASSIGNMENTS (64-PIN QFN) .....................................................................................................7
FIGURE 7. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................17
FIGURE 8. MDC/MDIO READ TIMING ........................................................................................................................................20
FIGURE 9. MDC/MDIO WRITE TIMING.......................................................................................................................................21
FIGURE 10. PHY RESET TIMING....................................................................................................................................................29
FIGURE 11. SWITCHING REGULATOR.............................................................................................................................................46
FIGURE 12. INPUT VOLTAGE OVERSHOOT <4V (GOOD)................................................................................................................48
FIGURE 13. INPUT VOLTAGE OVERSHOOT >4V (BAD) ..................................................................................................................48
FIGURE 14. CERAMIC 10µF 0603 (X5R) (GOOD) ..........................................................................................................................49
FIGURE 15. L=GLK2510P-2R2M, C=CERAMIC 4.7µF 0805 X5R TDK (RIPPLE 12.4MV) ...........................................................49
FIGURE 16. L=GLK2510P-2R2M, C=CERAMIC 10µF 0603 X5R YAGEO (RIPPLE 13.2MV) ......................................................50
FIGURE 17. L=GLK2510P-4R7M, C=CERAMIC 4.7µF 0805 X5R TDK (RIPPLE 12MV) ..............................................................50
FIGURE 18. L=GLK2510P-4R7M, C=CERAMIC 10µF 0603 X5R YAGEO (RIPPLE 11.2MV) ......................................................51
FIGURE 19. L=GTSD32P-2R2M, C=CERAMIC 4.7µF 0805 X5R TDK (RIPPLE 9.2MV)...............................................................51
FIGURE 20. CERAMIC 10µF (Y5V) (BAD)......................................................................................................................................52
FIGURE 21. ELECTROLYTIC 100µF (RIPPLE TOO HIGH).................................................................................................................52
FIGURE 22. GTSD32P-2R2M (GOOD)..........................................................................................................................................53
FIGURE 23. 1µH BEAD (BAD)........................................................................................................................................................53
FIGURE 24. SWITCHING REGULATOR EFFICIENCY MEASUREMENT CHECKPOINT ..........................................................................54
FIGURE 25. POWER SEQUENCE......................................................................................................................................................55
FIGURE 26. MDC/MDIO SETUP, HOLD TIME, AND VALID FROM MDC RISING EDGE TIME DEFINITIONS ....................................59
FIGURE 27. MDC/MDIO MANAGEMENT TIMING PARAMETERS ...................................................................................................59
FIGURE 28. MII INTERFACE SETUP/HOLD TIME DEFINITIONS .......................................................................................................60
FIGURE 29. MII TRANSMISSION CYCLE TIMING ............................................................................................................................60
FIGURE 30. MII RECEPTION CYCLE TIMING..................................................................................................................................61
FIGURE 31. GMII TIMING .............................................................................................................................................................62
FIGURE 32. RGMII TIMING MODES (FOR TXC) ...........................................................................................................................63
FIGURE 33. RGMII TIMING MODES (FOR RXC) ...........................................................................................................................64
Integrated 10/100/1000M Ethernet Transceiver
ix
Track ID: JATR-3375-16 Rev. 1.6
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