SK100E111PJ Просмотр технического описания (PDF) - Semtech Corporation
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SK100E111PJ Datasheet PDF : 6 Pages
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Description
.eatures
SK10/100E111
1:9 Differential
Clock Driver
PRELIMINARY
The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or single-
ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.
The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-
device, and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω , even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
sharing the same VCCO) as the pair(s) being used on
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• VBB Output
• Enable Input
• Extended 100E VEE Range of –4.2 to –5.5V
• Internal 75KΩ Input Pulldown Resistors
• Compatible with MC10/100E111
• Specified Over Industrial Temperature Range:
–40oC to +85oC
• ESD Protection of >4000V
• Available in 28-Lead PLCC Package
.unctional Block Diagram
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
Q4
The SK10/100E111 provides VBB output for either
Q4*
single-ended use or as a DC bias for AC coupling to
IN
the device. The VBB output pin should be used only
IN*
Q5
as a DC bias for the E111 as its current sink/source
Q5*
capability is limited. Whenever used, the VBB pin
EN*
should be bypassed to VCC via a 0.01 µF capacitor.
Q6
Q6*
Q7
Q7*
VBB
Q8
Q8*
Revision 2 /May 1, 2002
1
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