74AHC374PW Просмотр технического описания (PDF) - NXP Semiconductors.
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74AHC374PW Datasheet PDF : 17 Pages
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NXP Semiconductors
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Load and read register
Load register and disable outputs
Control
OE
CP
L
↑
L
↑
H
↑
H
↑
Input
Dn
l
h
l
h
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Z = high-impedance OFF-state.
7. Limiting values
Internal
flip-flop
L
H
L
H
Output
Q0 to Q7
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
VI
input voltage
IIK
input clamping current
IOK
output clamping current
IO
output current
VI < −0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
−0.5
+7.0
V
−0.5
+7.0
V
[1] −20
-
mA
[1] −20
+20
mA
−25
+25
mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = −40 °C to +125 °C
-
−75
−65
[2] -
+75
mA
-
mA
+150
°C
500
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
74AHC_AHCT374_3
Product data sheet
Rev. 03 — 12 June 2008
© NXP B.V. 2008. All rights reserved.
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