ATSAMA5D31A-CFU Просмотр технического описания (PDF) - Atmel Corporation

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ATSAMA5D31A-CFU

SMART ARM-based MPU

Atmel Corporation 

Table 2-1. Signal Description List (Continued)

Signal Name

Function

External Bus Interface - EBI

D0–D15

Data Bus

A0–A25

Address Bus

NWAIT

External Wait Signal

Static Memory Controller - SMC

NCS0–NCS3

Chip Select Lines

NWR0–NWR1

Write Signal

NRD

Read Signal

NWE

Write Enable

NBS0–NBS1

Byte Mask Signal

NANDOE

NAND Flash Output Enable

NANDWE

NAND Flash Write Enable

DDR2/LPDDR Controller

DDR_VREF

Reference Voltage

DDR_CALP

Positive Calibration Reference

DDR_CALN

Negative Calibration Reference

DDR_CK, DDR_CKN

DDR2 differential clock

DDR_CKE

DDR2 Clock Enable

DDR_CS

DDR2 Controller Chip Select

DDR_BA[2..0]

Bank Select

DDR_WE

DDR2 Write Enable

DDR_RAS, DDR_CAS

Row and Column Signal

DDR_A[13..0]

DDR2 Address Bus

DDR_D[31..0]

DDR2 Data Bus

DQS[3..0]

Differential Data Strobe

DQSN[3..0]

DQSN must be connected to DDR_VREF for DDR2 memories

DQM[3..0]

Write Data Mask

High Speed Multimedia Card Interface - HSMCIx [2..0]

MCI0_CK, MCI1_CK, MCI2_CK

Multimedia Card Clock

MCI0_CDA, MCI1_CDA, MCI2_CDA Multimedia Card Command

MCI0_DA[7..0]

Multimedia Card 0 Data

MCI1_DA[3..0]

Multimedia Card 1 Data

MCI2_DA[3..0)

Multimedia Card 2 Data

Type Active Level

I/O

—

Output

—

Input

Low

Output

Low

Output

Low

Output

Low

Output

Low

Output

Low

Output

Low

Output

Low

Input

Input

Input

Output

Output

Output

Output

Output

Output

Output

I/O

I/O

I/O

Output

—

—

—

—

High

Low

Low

Low

Low

—

—

—

—

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

6

SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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