ATSAMA5D31A-CFU Просмотр технического описания (PDF) - Atmel Corporation

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ATSAMA5D31A-CFU

SMART ARM-based MPU

Atmel Corporation 

Doc. Rev.

11121C Comments

Change

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Ref.

Section 41. “Two-wire Interface (TWI)”

Formatting and minor editorial changes throughout

rfo

Replaced “N” with “NA” as acronym for “Not Acknowledge” where needed

Section 41.6.2 “Power Management”: deleted rogue bullet “Enable the peripheral clock” below section heading rfo

Added missing “yes” and “no” in following figures:

8944/rfo

- Figure 41-18 “TWI Write Operation with Multiple Data Bytes with or without Internal Address”

- Figure 41-20 “TWI Read Operation with Single Data Byte and Internal Address”

- Figure 41-21 “TWI Read Operation with Multiple Data Bytes with or without Internal Address”

Section 41.10 “Slave Mode”: added Section 41.10.6 “Using the DMA Controller”

9055

Changed register acronym in Section 41.11 “Write Protection System” and renamed referenced field and flag

names

Table 41-7 “Register Mapping”: inserted reserved offset range 0x38–0xE0

8845

8944

Section 41.12.6 “TWI Status Register”: updated NACK (used in Master mode) bit description

9145

Section 41.12.11 “TWI Transmit Holding Register”: corrected access (was Read-write; is Write-only)

9050

Changed register acronym in Section 41.12.12 “TWI Write Protection Mode Register” and updated filed names 8845

and field descriptions

Changed register acronym in Section 41.12.13 “TWI Write Protection Status Register” and updated filed names 8845

and field descriptions

Section 42. “Synchronous Serial Controller (SSC)”

Minor editorial and formatting changes throughout

Section 42.9.17 “SSC Write Protect Mode Register”: updated WPKEY field description

8841

Section 43. “Debug Unit (DBGU)”: No changes

Section 44. “Universal Asynchronous Receiver Transmitter (UART)”

Minor editorial and formatting changes throughout

Changed register bit configuration value notations from ‘0 =’ to ‘0:’ and from ‘1 =’ to ‘1:’

rfo

Table 44-3 “Register Mapping”:

- inserted offset range 0x0040 - 0x00E8 (reserved)

- changed access from Read-write to Read/Write where applicable

8537

rfo

Section 45. “Universal Synchronous Asynchronous Receiver Transceiver (USART)”

Minor formatting and editorial changes throughout

Corrected Figure 45-22 “Parity Error” for stop bit value

8943

Table 45-10 “Maximum Timeguard Length Depending on Baud Rate”: replaced baud rate 33400 bit/s with

38400 bit/s

8943

Table 45-11 “Maximum Time-out Period”: replaced baud rate 33400 bit/s with 38400 bit/s

8943

Table 45-13 “IrDA Baud Rate Error”: added missing units of measure to column headers (“Bit/s” for Baud Rate rfo

and “µs” for Pulse Time)

Section 45.7.5.3 “IrDA Demodulator”: replaced instances of “T” with “t” when used to express time

rfo

Table 45-15 “Register Mapping”:

8943

- inserted offset range 0x0054–0x005C (reserved)

- inserted offset range 0x0060–0x00E0 (reserved)

- replaced range 0x5C–0xFC with range 0x00EC–0x00FC (reserved)

Section 45.8.22 “USART Write Protect Mode Register”: updated WPKEY field description

8791

SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

1901

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