EVAL-AD5700-1EBZ Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание

производитель

EVAL-AD5700-1EBZ

Low Power HART Modem

Analog Devices 

AD5700/AD5700-1

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter

VCC to GND

IOVCC to GND

Digital Inputs to DGND

Digital Output to DGND

HART_OUT to AGND

HART_IN to AGND

ADC_IP

AGND to DGND

Operating Temperature Range (TA)

Industrial

Storage Temperature Range

Junction Temperature (TJ MAX)

Power Dissipation

Lead Temperature,

Soldering

ESD

Human Body Model

(ANSI/ESDA/JEDEC JS-001-

2010)

Field Induced Charge Model

(JEDEC JESD22_C101E)

Machine Model

(ANSI/ESD S5.2-2009)

Rating

−0.3 V to +7 V

−0.3 V to +7 V

−0.3 V to IOVCC + 0.3 V or

+7 V (whichever is less)

−0.3 V to IOVCC + 0.3 V or

+7 V (whichever is less)

−0.3 V to +2.5 V

−0.3 V to VCC + 0.3 V or

+7 V (whichever is less)

−0.3 V to VCC + 0.3 V or

+7 V (whichever is less)

−0.3 V to +0.3 V

−40°C to +125°C

−65°C to +150°C

150°C

(TJ MAX – TA)/θJA

JEDEC industry standard

J-STD-020

8 kV

1.5 kV

400 V

Data Sheet

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type

θJA1

θJC

24-Lead LFCSP

56

3

Unit

°C/W

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with thermal vias. See JEDEC JESD51.

ESD CAUTION

Rev. G | Page 6 of 24

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