OR2C10A3S208I-DB Просмотр технического описания (PDF) - Lattice Semiconductor

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OR2C10A3S208I-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Table 4. ORCA Series 2TB System Performance

Function

#

PFUs

Speed Grade

-7

-8

Unit

16-bit loadable up/down

4 131.6 149.3 MHz

counter

16-bit accumulator

8 x 8 parallel multiplier:

— Multiplier mode,

S unpipelined1

— ROM mode, unpipelined2

E — Multiplier mode, pipelined3

32 x 16 RAM:

— Single port (read and write/

IC cycle)4

— Single port5

D — Dual port6

36-bit parity check (internal)

V E 32-bit address decode

(internal)

4 131.6 149.3 MHz

22 37.7 44.8 MHz

9 103.1 120.5 MHz

44 123.5 142.9 MHz

9

57.5 69.4 MHz

9

97.7 112.4 MHz

16 97.7 112.4 MHz

4

6.1

5.1

ns

3.25 4.8

4.0

ns

E 1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.

U 2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.

3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).

4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address

D multiplexer.

IN 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address

multiplexer.

SELDEICSTCONT 6. Implemented using 16 x 2 synchronous dual-port RAM mode.

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