OR2C10A3S208I-DB Просмотр технического описания (PDF) - Lattice Semiconductor
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OR2C10A3S208I-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Table of Contents
Contents
Page Contents
Page
Features ....................................................................1
Boundary-Scan Instructions................................. 57
Description .................................................................3
ispLEVER Development System Overview ...............7
Architecture ...............................................................7
Programmable Logic Cells ........................................7
S Programmable Function Unit .................................7
Look-Up Table Operating Modes ..........................9
Latches/Flip-Flops ...............................................17
E PLC Routing Resources ......................................19
PLC Architectural Description ..............................24
Programmable Input/Output Cells ...........................27
IC Inputs ...................................................................27
Outputs ................................................................28
D 5 V Tolerant I/O (OR2TxxB) ................................29
PCI Compliant I/O ................................................29
V PIC Routing Resources .......................................30
E PIC Architectural Description ...............................31
PLC-PIC Routing Resources ...............................32
E Interquad Routing ....................................................34
U Subquad Routing (OR2C40A/OR2T40A Only) ....36
PIC Interquad (MID) Routing ...............................38
D Programmable Corner Cells ....................................39
IN Programmable Routing ........................................39
Special-Purpose Functions ..................................39
Clock Distribution Network ....................................... 39
T Primary Clock ......................................................39
T Secondary Clock .................................................40
Selecting Clock Input Pins ...................................41
C FPGA States of Operation .......................................42
N Initialization ..........................................................42
Configuration .......................................................43
E Start-Up ...............................................................44
O Reconfiguration ...................................................44
L Partial Reconfiguration ........................................45
Other Configuration Options ................................45
E C Configuration Data Format ......................................45
Using ispLEVER to Generate
Configuration RAM Data ...................................46
S IS Configuration Data Frame ...................................46
Bit Stream Error Checking .......................................49
FPGA Configuration Modes .....................................49
D Master Parallel Mode ...........................................49
ORCA Boundary-Scan Circuitry ..........................58
ORCA Timing Characteristics ..................................62
Estimating Power Dissipation ..................................63
OR2CxxA .............................................................63
OR2TxxA .............................................................65
OR2T15B and OR2T40B .....................................67
Pin Information ........................................................68
Pin Descriptions ...................................................68
Package Compatibility .........................................70
Compatibility with Series 3 FPGAs .......................72
Package Thermal Characteristics ..........................128
Theta JA ............................................................128
Theta JC ............................................................128
Theta JC ............................................................128
Theta JB ............................................................128
Package Coplanarity .............................................129
Package Parasitics ................................................129
Absolute Maximum Ratings ...................................131
Recommended Operating Conditions ...................131
Electrical Characteristics .......................................132
Timing Characteristics ...........................................134
Series 2 ..............................................................162
Measurement Conditions .......................................171
Output Buffer Characteristics ................................172
OR2CxxA ...........................................................172
OR2TxxA ...........................................................173
OR2TxxB ...........................................................174
Package Outline Drawings ....................................175
Terms and Definitions ........................................175
84-Pin PLCC ......................................................176
100-Pin TQFP ....................................................177
144-Pin TQFP ....................................................178
160-Pin QFP ......................................................179
208-Pin SQFP ....................................................180
208-Pin SQFP2 ..................................................181
240-Pin SQFP ....................................................182
240-Pin SQFP2 ..................................................183
256-Pin PBGA ...................................................184
304-Pin SQFP ....................................................185
304-Pin SQFP2 ..................................................186
352-Pin PBGA ...................................................187
Master Serial Mode .............................................50
432-Pin EBGA ...................................................188
Asynchronous Peripheral Mode .......................... 51 Ordering Information .............................................189
Synchronous Peripheral Mode ............................51
Slave Serial Mode ...............................................52
Slave Parallel Mode .............................................52
Daisy Chain .........................................................53
Special Function Blocks ..........................................54
Single Function Blocks ........................................54
Boundary Scan ....................................................56
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