AD6643 Просмотр технического описания (PDF) - Analog Devices
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AD6643 Datasheet PDF : 40 Pages
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Data Sheet
Timing Diagrams
VIN
CLK+
CLK–
DCO–
DCO+
PARALLEL INTERLEAVED
D0
(LSB)
.
CHANNEL A AND .
CHANNEL B .
D11
(MSB)
AD6643
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
tPD
CH A CH B
N – 10 N – 10
CH A
N–9
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CH A CH B
N – 10 N – 10
CH A
N–9
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CHANNEL MULTIPLEXED 0/D0±
(ODD/EVEN) MODE (LSB)
.
CHANNEL A
.
.
D9/D10±
(MSB)
CHANNEL MULTIPLEXED 0/D0±
(ODD/EVEN) MODE (LSB)
.
CHANNEL B ..
D9/D10±
(MSB)
0
CH A0
N – 10 N – 10
0
N–9
CH A0
N–9
0
N–8
CH A0
N–8
0
N–7
CH A0
N–7
0
N–6
CH A9 CH A10 CH A9 CH A10 CH A9 CH A10 CH A9 CH A10 CH A9
N – 10 N – 10 N – 9
N–9
N–8 N–8
N–7
N–7
N–6
0
CH B0
N – 10 N – 10
0
N–9
CH B0
N–9
0
N–8
CH B0
N–8
0
N–7
CH B0
N–7
0
N–6
CH B9 CH B10 CH B9 CH B10 CH B9 CH B10 CH B9 CH B10 CH B9
N – 10 N – 10 N – 9
N–9
N–8 N–8
N–7
N–7
N–6
Figure 2. LVDS Modes for Data Output Timing Latency. NSR Disabled (Enabling NSR Adds an Additional Three Clock Cycles of Latency)
CLK+
SYNC
tSSYNC
tHSYNC
Figure 3. SYNC Timing Inputs
Rev. C | Page 9 of 40
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