AD6643 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD6643 Datasheet PDF : 40 Pages
| |||
AD6643
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.75 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (NSR Disabled)
IDRVDD1 (NSR Enabled—22% Mode)
IDRVDD1 (NSR Enabled—33% Mode)
POWER CONSUMPTION
Sine Wave Input1 (DRVDD = 1.8 V,
NSR Disabled)
Sine Wave Input1 (DRVDD = 1.8 V,
NSR Enabled—22% Mode)
Sine Wave Input1 (DRVDD = 1.8 V,
NSR Enabled—33% Mode)
Standby Power4
Power-Down Power
AD6643-200
AD6643-250
Temperature Min
Typ
Max
Min
Typ
Max
Unit
Full
11
11
Bits
Full
Guaranteed
Guaranteed
Full
±10
±10
mV
Full
+2/−6
−5/+3
% FSR
Full
±0.1
±0.25
±0.1
±0.4
LSB
Full
±0.2
±0.25
±0.2
±0.4
LSB
25°C
±13
±13
mV
25°C
−2/+3.5
−2.5/+3.5 % FSR
Full
±15
Full
±87
±15
ppm/°C
±87
ppm/°C
25°C
0.614
0.614
LSB rms
Full
1.75
Full
2.5
Full
20
Full
0.9
1.75
V p-p
2.5
pF
20
kΩ
0.9
V
Full
1.7
1.8
1.9
1.7
1.8
1.9
V
Full
1.7
1.8
1.9
1.7
1.8
1.9
V
Full
238
260
256
275
mA
Full
154
215
180
215
mA
Full
172
206
mA
Full
186
218
mA
Full
706
855
785
873
mW
Full
738
832
mW
Full
765
853
mW
Full
90
Full
10
90
mW
10
mW
1 Measured using a 10 MHz, 0 dBFS sine wave, and 100 Ω termination on each LVDS output pair.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured using a dc input and the CLK± pins inactive (set to AVDD or AGND).
Rev. C | Page 4 of 40
Share Link: 