AD6643 Просмотр технического описания (PDF) - Analog Devices

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AD6643

Dual IF Receiver

Analog Devices 

AD6643

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

ADC DC Specifications................................................................. 4

ADC AC Specifications ................................................................. 5

Digital Specifications—AD6643-200/AD6643-250..................... 6

Switching Specifications ................................................................ 8

Timing Specifications—AD6643-200/AD6643-250................ 8

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................ 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 15

Equivalent Circuits ......................................................................... 20

Theory of Operation ...................................................................... 21

ADC Architecture ...................................................................... 21

Analog Input Considerations.................................................... 21

Voltage Reference ....................................................................... 23

Clock Input Considerations...................................................... 23

Power Dissipation and Standby Mode .................................... 24

Digital Outputs ........................................................................... 25

ADC Overrange (OR)................................................................ 25

Noise Shaping Requantizer (NSR) ............................................... 26

22% BW Mode (>40 MHz at 184.32 MSPS)........................... 26

33% BW Mode (>60 MHz at 184.32 MSPS)........................... 27

Channel/Chip Synchronization.................................................... 28

Serial Port Interface (SPI).............................................................. 29

Configuration Using the SPI..................................................... 29

Hardware Interface..................................................................... 29

SPI Accessible Features.............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Memory Map Register Table..................................................... 32

Memory Map Register Description ......................................... 35

Applications Information .............................................................. 36

Design Guidelines ...................................................................... 36

Outline Dimensions ....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

11/12—Rev. B to Rev. C

Changes to Features Section.............................................................1

Change to Table 1 ................................................................................

Changes to Table 4.............................................................................8

Changes to Reading the Memory Map Register Table

Section ...............................................................................................31

Deleted Registers 0x0E, 0x24, and 0x25, Table 14.......................33

Change to Memory Map Register Description Section..............36

Updated Outline Dimensions ........................................................37

6/12—Rev. A to Rev. B

Changes to Features.......................................................................... 1

Changes to Full Power Bandwidth Parameter, Deleted Noise

Bandwidth Parameter, Changes to Endnote 3; Table 2 ............... 6

Added Figure 20 to Figure 33; Renumbered Sequentially ........ 17

Changes to Figure 52...................................................................... 24

Updated Outline Dimensions ....................................................... 35

9/11—Rev. 0 to Rev. A

Added 250 MSPS Speed Grade Throughout................................. 1

Changes to Table 1............................................................................ 4

Changes to Table 2............................................................................ 5

Changes to Table 4............................................................................ 8

Changes to Figure 2...........................................................................9

Change to OEB Pin Description, Table 8 .................................... 12

Changes Figure 5 and Table 9 ....................................................... 13

Changes to Typical Performance Characteristics Conditions

Summary ......................................................................................... 15

Added AD6643-200 Throughout ................................................. 15

Changes to Figure 24 and Figure 25 ............................................ 18

Changes to Theory of Operation Section.................................... 19

Changes to Timing Section ........................................................... 23

Added ADC Overrange (OR) Section ......................................... 23

Changed Frequency (Hz) to Frequency (MHz) in Figure 39,

Figure 40, and Figure 41 ................................................................ 24

Changed Frequency (Hz) to Frequency (MHz) in Figure 42,

Figure 43, and Figure 44 ................................................................ 25

Changes to Channel/Chip Synchronization Section ................. 26

Changed 0x59 to 0x3E Throughout............................................. 29

Changes to 0x02, Bits[5:4] and 0x16, Bit 5 in Table 14 ............. 30

Deleted 0x59, Table 14 ................................................................... 32

Deleted SYNC Pin Control (Register 0x59) Section.................. 33

Changes to Ordering Guide .......................................................... 35

4/11—Revision 0: Initial Version

Rev. C | Page 2 of 40

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