AD5421 Просмотр технического описания (PDF) - Analog Devices
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AD5421 Datasheet PDF : 36 Pages
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AD5421
Parameter1
REGOUT OUTPUT
Output Voltage
Output Voltage TC3
Output Voltage Accuracy
Externally Available Current3, 6
Short-Circuit Current
Line Regulation3
Load Regulation3
Inductive Load
Capacitive Load
ADC ACCURACY
Die Temperature
VLOOP Input
DVDD OUTPUT
Output Voltage
Externally Available Current3, 6
Short-Circuit Current
Load Regulation
DIGITAL INPUTS3
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
Input Current
Pin Capacitance
DIGITAL OUTPUTS3
SDO Pin
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
High Impedance Output
Capacitance
FAULT Pin
Output Low Voltage, VOL
Output High Voltage, VOH
FAULT THRESHOLDS
ILOOP Under
ILOOP Over
Temp 140°C
Temp 100°C
VLOOP 6V
VLOOP 12V
Min
Typ
1.8
110
−4
±2
3.15
23
500
10
8
50
2
10
±5
±1
3.17
3.3
3.15
7.7
45
0.7 × IODVDD
0.21
0.63
1.46
−0.015
5
Max
Unit
12
V
ppm/°C
+4
%
mA
mA
µV/V
µV/V
mV/mA
mH
µF
°C
%
3.48
V
mA
mA
mV/mA
V
0.25 × IODVDD V
V
V
V
+0.015
µA
pF
IODVDD − 0.5
−0.01
5
0.4
V
V
+0.01
µA
pF
IODVDD − 0.5
0.4
V
V
ILOOP − 0.01% FSR
mA
ILOOP + 0.01% FSR
mA
133
°C
90
°C
0.3
V
0.6
V
Data Sheet
Test Conditions/Comments
Voltage regulator output
See Table 10
Assuming 4 mA flowing in the loop
and during HART communications
Internal NMOS
External NMOS
Stable operation
Recommended operation
Can be overdriven up to 5.5 V
Assuming 4 mA flowing in the loop
and during HART communications
Measured at 0 mA and 3 mA loads
SCLK, SYNC, SDIN, LDAC
IODVDD = 1.8 V
IODVDD = 3.3 V
IODVDD = 5.5 V
Per pin
Per pin
Fault removed when temperature
≤ 125°C
Fault removed when temperature
≤ 85°C
Fault removed when VLOOP ≥ 0.4 V
Fault removed when VLOOP ≥ 0.7 V
Rev. H | Page 6 of 36
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