MAX19708 Просмотр технического описания (PDF) - Maxim Integrated
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MAX19708 Datasheet PDF : 37 Pages
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10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CS High to DOUT Low (Aux-ADC
Conversion Time)
tCONV
Bit AD0 set, no averaging (see Table 15),
fCLK = 11MHz,
CLK divider = 4 (see Table 16)
DOUT Low to CS Setup Time
tDCS
Bit AD0, AD10 set
SCLK Low to DOUT Data Out
tCD
Bit AD0, AD10 set
CS High to DOUT High Impedance
tCHZ
Bit AD0, AD10 set
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 8)
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
4.36
µs
200
ns
14.5
ns
200
ns
82.2
µs
29
From idle to Rx mode with CLK present
during idle, ADC settles to within 1dB SINAD
9.6
Idle Wake-Up Time (With CLK)
tWAKE,ST0
µs
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
7.6
From standby to Rx mode, ADC settles to
17.5
within 1dB SINAD
Standby Wake-Up Time
tWAKE,ST1
µs
From standby to Tx mode, DAC settles to
24
10 LSB error
Enable Time from Tx to Rx (Ext2-Tx
to Ext2-Rx, Ext4-Tx to Ext4-Rx, and tENABLE, RX ADC settles to within 1dB SINAD
SPI4-Tx to SPI3-Rx States)
500
ns
Enable Time from Rx to Tx (Ext1-Rx
to Ext1-Tx, Ext4-Rx to Ext4-Tx, and
SPI3-Rx to SPI4-Tx States)
tENABLE, TX DAC settles to within 10 LSB error
500
ns
Enable Time from Tx to Rx (Ext1-Tx
to Ext1-Rx, Ext3-Tx to Ext3-Rx, and tENABLE, RX ADC settles to within 1dB SINAD
SPI1-Tx to SPI1-Rx States)
8.1
µs
Enable Time from Rx to Tx (Ext2-Rx
to Ext2-Tx, Ext3-Rx to Ext3-Tx, and
SPI1-Rx to SPI2-Tx States)
tENABLE,TX DAC settles to within 10 LSB error
7.0
µs
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally)
Positive Reference
VREFP - VCOM
0.256
V
Negative Reference
VREFN - VCOM
-0.256
V
Common-Mode Output Voltage
VCOM
VDD / 2
- 0.15
VDD / 2
VDD / 2
+ 0.15
V
Maximum REFP/REFN/COM
Source Current
ISOURCE
2
mA
8 _______________________________________________________________________________________
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