MAX19705ETM Просмотр технического описания (PDF) - Maxim Integrated

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производитель

MAX19705ETM

10-Bit, 7.5Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

10-Bit, 7.5Msps, Ultra-Low-Power

Analog Front-End

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =

CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN)

Input High Threshold

VINH

Input Low Threshold

VINL

Input Leakage

DIIN

D0–D9, CLK, SCLK, DIN, CS, T/R,

SHDN = OGND or OVDD

Input Capacitance

DCIN

DIGITAL OUTPUTS (D0–D9, DOUT)

Output-Voltage Low

VOL

ISINK = 200µA

Output-Voltage High

VOH

ISOURCE = 200µA

Tri-State Leakage Current

ILEAK

Tri-State Output Capacitance

COUT

MIN TYP MAX UNITS

0.7 x OVDD

V

0.3 x OVDD V

-1

+1

µA

5

pF

0.2 x OVDD V

0.8 x OVDD

V

-1

+1

µA

5

pF

Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are

guaranteed by design and characterization.

Note 2: Guaranteed by design and characterization.

Note 3: The minimum clock frequency (fCLK) for the MAX19705 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequency

(ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 1.5MHz / 128

= 11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI. The maximum

conversion time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 1.5MHz = 1024µs.

Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude

of the digital outputs. SINAD and THD are calculated using HD2 through HD6.

Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second

channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel

FFT test tone.

Note 6: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output

signals using a sine-wave fit.

Typical Operating Characteristics

(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =

CCOM = 0.33µF, TA = +25°C, unless otherwise noted.)

Rx ADC CHANNEL-IA

Rx ADC CHANNEL-IA FFT PLOT

Rx ADC CHANNEL-QA FFT PLOT

TWO-TONE FFT PLOT

0

fCLK = 7.5MHz

-10 fIA = 1.8063354MHz

-20

AIA = -0.561dB

8192-POINT

-30 DATA RECORD

-40

-50

0

fCLK = 7.5MHz

-10 fQA = 1.8063354MHz

-20

AQA = -0.533dB

8192-POINT

-30 DATA RECORD

-40

-50

0

fCLK = 7.5MHz

-10 f1 = 2.0MHz

-20

f2 = 2.1MHz

AIA = -7dBFS

-30 PER TONE

8192-POINT

-40 DATA RECORD

-50

f1

f2

-60

-60

2

-60

-70

-80

5

9

48

3

2

7 10 6

-70

48

95

3 7 10 6

-80

-70

-80

-90

-90

-90

-100

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

FREQUENCY (MHz)

-100

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

FREQUENCY (MHz)

-100

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

FREQUENCY (MHz)

_______________________________________________________________________________________ 9

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