MAX19705ETM Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
производитель
MAX19705ETM Datasheet PDF : 37 Pages
| |||
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Q-DAC DATA to CLK Rise Setup
Time
tDSQ Figure 5 (Note 2)
10
ns
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold
Time
tDHI
tDHQ
Figure 5 (Note 2)
Figure 5 (Note 2)
0
ns
0
ns
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 2)
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
50
%
±15
%
2
ns
10
ns
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to CS Setup Time
CS High Pulse Width
CS High to DOUT Active High
tDS
tDH
tCH
tCL
tCP
tCS
tCSW
tCSD
Bit AD0 set
10
ns
0
ns
25
ns
25
ns
50
ns
10
ns
80
ns
200
ns
CS High to DOUT Low (Aux-ADC
Conversion Time)
tCONV
Bit AD0 set, no averaging (see Table 14),
fCLK = 7.5MHz,
CLK divider = 2 (see Table 15)
3.2
µs
DOUT Low to CS Setup Time
tDCS
Bit AD0, AD10 set
SCLK Low to DOUT Data Out
tCD
Bit AD0, AD10 set
CS High to DOUT High Impedance
tCHZ
Bit AD0, AD10 set
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
200
ns
14.5
ns
200
ns
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
84.9
Shutdown Wake-Up Time
tWAKE,SD
µs
From shutdown to Tx mode, DAC settles to
within 10 LSB error
26.4
From idle to Rx mode with CLK present
10.9
during idle, ADC settles to within 1dB SINAD
Idle Wake-Up Time (With CLK)
tWAKE,ST0
µs
From idle to Tx mode with CLK present
6.0
during idle, DAC settles to 10 LSB error
From standby to Rx mode, ADC settles to
17.6
within 1dB SINAD
Standby Wake-Up Time
tWAKE,ST1
µs
From standby to Tx mode, DAC settles to
25
10 LSB error
_______________________________________________________________________________________ 7
Share Link: 