AD9361 Просмотр технического описания (PDF) - Analog Devices
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AD9361 Datasheet PDF : 36 Pages
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Data Sheet
Parameter
WiMAX 10
Single Port
TDD RX
TDD TX
FDD
WiMAX 20
Dual Port
FDD
P-P56
75 mV Differential Output
300 mV Differential Output
450 mV Differential Output
Table 4. VDD_INTERFACE = 2.5 V
Parameter
SLEEP MODE
1RX, 1TX, DDR
LTE10
Single Port
Dual Port
LTE20
Dual Port
2RX, 2TX, DDR
LTE3
Dual Port
LTE10
Single Port
Dual Port
LTE20
Dual Port
GSM
Dual Port
WiMAX 8.75
Dual Port
WiMAX 10
Single Port
TDD RX
TDD TX
FDD
WiMAX 20
Dual Port
FDD
P-P56
75 mV Differential Output
300 mV Differential Output
450 mV Differential Output
AD9361
Min
Typ
Max
Unit
Test Conditions/Comments
0.7
mA
22.4 MHz data clock, CMOS
5.6
mA
22.4 MHz data clock, CMOS
6.0
mA
44.8 MHz data clock, CMOS
10.7
mA
44.8 MHz data clock, CMOS
14.0
mA
240 MHz data clock, LVDS
35.0
mA
240 MHz data clock, LVDS
47.0
mA
240 MHz data clock, LVDS
Min
Typ
Max
Unit
Test Conditions/Comments
150
µA
Power applied, device disabled
6.5
mA
30.72 MHz data clock, CMOS
6.0
mA
15.36 MHz data clock, CMOS
11.5
mA
30.72 MHz data clock, CMOS
3.0
mA
7.68 MHz data clock, CMOS
11.5
mA
61.44 MHz data clock, CMOS
10.0
mA
30.72 MHz data clock, CMOS
20.0
mA
61.44 MHz data clock, CMOS
0.5
mA
1.08 MHz data clock, CMOS
7.3
mA
20 MHz data clock, CMOS
1.3
mA
22.4 MHz data clock, CMOS
8.0
mA
22.4 MHz data clock, CMOS
8.7
mA
44.8 MHz data clock, CMOS
15.3
mA
44.8 MHz data clock, CMOS
26.0
mA
240 MHz data clock, LVDS
45.0
mA
240 MHz data clock, LVDS
58.0
mA
240 MHz data clock, LVDS
Rev. F | Page 9 of 36
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