R5H30211 Просмотр технического описания (PDF) - Renesas Electronics
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R5H30211 Datasheet PDF : 19 Pages
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R5H30211
Item
On-chip memory
Random number
generator (RNG)
Watchdog timer (WDT)
Firewall management
unit (FMU)
Interval timer
(TMR1/TMR2)
Modular multiplication
coprocessor
Interrupt
Specification
• EEPROM: 16 kbytes + 2 kbytes (64 bytes × (256 + 32) pages)
Writing function by dedicated transfer instruction from CPU
Page write (1 byte to 64 bytes) and erase
Protected against accidental writing and erasing
Generates an EWE interrupt before an EEPMOV.B instruction is executed
On-chip high voltage generation circuit for writing and erasing
Built-in oscillator and timer
Write/erase time (maximum value): 3 ms (rewrite), 1.5 ms (erase)
Rewrite endurance: 1 × 105 times (-20°C to +75°C)
Data retention time: 10 years
• ROM: 112 kbytes
• RAM: 4 kbytes
• Generates 16-bit random numbers.
• Interrupts can be generated on completion of random number generation.
• One of four random number generation times can be selected.
• Generates a UDF interrupt constantly at any interval.
• Stops the on-chip functions when the halt flag is set.
• One of four counter clock sources can be selected.
• Monitors memory access address of the user application.
• Monitoring function of access between memory (monitors program execution on RAM and
EEPROM)
• Generates an interval interrupt constantly at any interval.
• One of four counter clock sources can be selected.
• Countable at a maximum of 4.5 seconds.
• Modular multiplication (ABR-1 mod N + kN, etc.)
• Modular exponentiation (XY mod N) with CPU control
• Programmable data length: 160, 192, 256, 320, 384, 448, 512, 576, 640, 768, 896, or 1024
bits
• Four operations:
Three types of modular multiplications:
ABR-1 mod N + kN, A2R-1 mod N + kN, and AR-1 mod N + kN
One type of multiplication:
A × N (A is fixed to 32 bits, and the maximum data length of operation results is 1024
bits)
• 512-byte special-purpose registers
Four 128-byte (1024-bit) registers (Registers A, B, N, and W)
Can be used as RAM for the CPU when coprocessor calculations are not being
performed
• Interrupt request to the CPU when the coprocessor completes calculation
• Built-in multiplier allows up to 4× speed operation.
• Four external interrupt pins: P1/IRQ to P4/IRQ
Used for interrupt input in sleep modes 1 and 2
Same exception handling vector is assigned to the four pins
• Internal interrupts (excluding TRAPA instruction)
Ten interrupt sources: EWE, UDF, RNG, TMR1, TMR2, IIC2, SSU, modular
multiplication coprocessor, voltage monitor circuit, and clock multiplier
Notes: 1. When using I/O ports and sleep mode 1 is entered, clear DDR to 0 to use the pins as
I/O input port pins before executing the SLEEP instruction.
2. Execute MOV instruction instead of bit manipulation when writing to bits DDR7 to
DDR4.
3. Set the corresponding bit of IOIRQS to 1 when using the external interrupt on
returning from sleep modes 1 and 2.
REJ03B0259-0110 Rev.1.10 Jun. 05, 2009
Page 2 of 17
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