R5H30211 Просмотр технического описания (PDF) - Renesas Electronics

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R5H30211

Renesas Microcomputer

Renesas Electronics 

R5H30211

Table 6 Clock Cycle Times

Conditions: VCC = 1.8 to 3.6 V, unless otherwise specified.

Item

CPU is driven by an external clock

divided by 2

CPU is driven at the same clock rate

as the external clock

CPU is driven by an external clock

doubled by PLL

CPU is driven at the same clock rate

as the external clock (doubled by PLL

and then divided by 2)

Coprocessor Operation

Min.

Stopped or normal speed operation

0.2

(Vcc = 1.8 to 3.0V)

Stopped or normal speed operation (Vcc = 3.0 0.125

to 3.6V)

Double speed operation

0.2

(Vcc = 1.8 to 3.0V)

Double speed operation

(Vcc = 3.0 to 3.6V)

0.125

Quad speed operation

0.2

Stopped or normal speed operation

0.2

(Vcc = 1.8 to 3.0V)

Stopped or normal speed operation

(Vcc = 3.0 to 3.6V)

0.125

Double speed operation

0.2

(Vcc = 1.8 to 3.0V)

Double speed operation

(Vcc = 3.0 to 3.6V)

0.125

Quad speed operation

0.2

Stopped or normal speed operation

0.2

(Vcc = 1.8 to 3.0V)

Stopped or normal speed operation

(Vcc = 3.0 to 3.6V)

0.125

Double speed operation

0.2

(Vcc = 1.8 to 3.0V)

Double speed operation

(Vcc = 3.0 to 3.6V)

0.125

Quad speed operation

0.2

Stopped or normal speed operation

0.2

Double speed operation

0.2

Quad speed operation

0.2

Typ.

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max. Unit

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

1.0 µs

tcyc

VIH

VIH

CLK

VIL

tCH

VIL

VIL

tCr

tCf

tCL

Figure 4.1 CLK Input Waveform

φRC

φ

Same as on-chip oscillator

clock

φ

Half of on-chip oscillator clock

tscyc

tscyc

Figure 4.2 System Clock Timing (Internal clock)

REJ03B0259-0110 Rev.1.10 Jun. 05, 2009

Page 10 of 17

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