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53C810

PCI-SCSI I/O Processor

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PRELIMINARY

Chapter One

Introduction

apter One

SCSI 1/0 Processor Description

General Description

The 53C810 PCI-SCSI 110 Processor is based on

the NCR 53C7XX 110 Processor architecture with

a Peripheral Component Interconnect (pCl) front

end. The NCR 53C81 0 integrates a high-perfor-

mance SCSI core and a PCI bus master DMA core

with a SCSI SCRIPTS processor to accommodate

the flexibility requirements of not only SCSI-1 and

SCSI-2, but future SCSI standards as well. The

53C8-l0 solves the protocol overhead problems that

have plagued previous intelligent and non-intelli-

gent adapter designs.

The 53C810 has been designed to "gluelessly" con-

nect to the emerging industry standard PCI Bus. An

entire SCSI solution, including a SCSI oscillator

(40MHz), termination electronics, and an external

connector (Figure 1-1), can be implemented on less

than four square inches of space on the

motherboard. In addition to the required PCI pins,

the 53C810 provides two other signals useful in

adapter plug-in card designs.

The chip is fully supported by NCR SDMS (SCSI

Device Management System) software based on the

industry standard Common Access Method

(CAM). The 53C810 is packaged in a 100-pin

PQFP package, can operate the SCSI bus at

5 MB/s asynchronously or 10 MB/s synchronously,

and burst data to the host at full PCI speeds.

The 53C810 is designed to implement a.multi-

threaded I/O algorithm with a minimum ofproces-

sor intervention. The 53C810 provides automatic

relocation of SCRIPTS, and requires no dynamic

alteration of SCRIPTS instructions at the start of an

110 operation. All of the SCRIPTS code may be

placed in PROM. The 53C810 allows easy firm-

ware upgrades and is supported by advanced

SCRIPTS commands.

NCR TolerANT~echnology

The 53C810 features NCR TolerANT technology,

which includes active negation on the SCSI drivers

and input signal filtering on the SCSI receivers.

Active negation causes the SCSI REQ, ACK, Data,

and Parity signals to be actively driven high. Active

negation is enabled by setting bit 7 in the STEST3

register.

TolerANT receiver technology improves data integ-

rity in unreliable cabling environments, where other

devices would be subject to data corruption.

TolerANT receivers filter the SCSI bus signal to

eliminate unwanted transitions without the long

signal delay associated with RC-type input fIlters.

This improved driver and receiver technology helps

eliminate the double clocking of data, the single

biggest reliability issue with SCSI operations. The

fIltering period is user-selectable at 30 or 60 ns,

with bit 1 in the STEST2 register.

The benefits of TolerANT include increased

immunity to noise when the signal is going high,

increased performance due to balanced duty

cycles, and improved fast SCSI transfer rates.

TolerANT is compatible with both the Alterna-

tive One and Alternative Two termination

schemes proposed by the American National

Standards Institute.

NCR 53C810 Data Manual

1-1

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