STE2002 Просмотр технического описания (PDF) - STMicroelectronics
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STE2002 Datasheet PDF : 61 Pages
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STE2002
Display data RAM
Figure 12. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=1)
BANK 0
BANK 1
BANK 2
127 126 125 124
X CARR
Y CARR
BANK 11
BANK 12
321
Figure 13. Data RAM Byte organization with D0 = 0
MSB
LSB
0
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
124 125 126 127
Figure 14. Data RAM Byte organization with D0 = 1
LSB
MSB
0
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
124 125 126 127
Figure 15. Memory rows vs. row drivers mapping with MY=0, MUX81, icon mode=0,1
ROW DRIVER ROW DRIVER
ICON MODE=1 ICON MODE=0
PHYSICAL MEMORY ROW
0123
R0
R0
ROW 0
R1
R1
ROW 1
R2
R2
ROW 2
R3
R3
ROW 3
124 125 126 127
Y-CARRIAGE
R 79
R 80
ICON
R 79
ROW 79
R 80
ROW 80
ICON ROW
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