STE2002 Просмотр технического описания (PDF) - STMicroelectronics

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STE2002

81 x 128 single-chip LCD controller/driver

STMicroelectronics 

Display data RAM

3

Display data RAM

STE2002

The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized

into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be

used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided

(see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y12 (Vertical).

When writing to RAM, four addressing mode are provided:

• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the

left of the memory map. The X pointer is increased after each byte written. After the last

column address (X=X-Carriage), Y address pointer is set to jump to the following bank and

X restarts from X=0. (Fig. 6)

• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left

of the memory map. The Y pointer is increased after each byte written. After the last Y bank

address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from

Y=0 (Fig. 7).

• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the

right of the memory map. The X pointer is increased after each byte written. After the last

column address (X=X-Carriage), Y address pointer is set to jump to the next bank and X

restarts from X=0 (fig. 8).

• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the

right of the memory map. The Y pointer is increased after each byte written. After the last Y

bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts

from Y=0 (fig. 9).

After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always

jump to the cell with address (X;Y) = (0;0) (Fi. 10, 11, 12 & 13).

Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.14) or on the

bottom (D0=1, Fig. 15).

The STE2002 provides also means to alter the normal output addressing. A mirroring of the

Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect

the content of the memory RAM. It is only related to the visualization process.

When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON

Mode=0 the Icon Row is like the other graphic lines and is mirrored and scrolled.

Four are the multiplex ratio available when the partial display mode is disabled (MUX 33,

MUX 49, MUX 65 and MUX 81).

Only a subset of writable rows are output on Row drivers.

When Y-Carriage<MUX/8, if Mux 65 is selected only the first 65 memory rows are

visualized, if Mux 49 is selected only the first 49 memory rows are visualized, if Mux 33 is

selected only the first 33 memory rows are visualized. All unused Row and Column drivers

must be left floating.

When Y-Carriage<MUX/8, the icon Bank is located to BANK 10 in MUX 81 Mode, to

BANK8 in MUX 65 Mode, to BANK 6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode.

When Y-Carriage>MUX/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to

select which lines of DDRAM are connected on the output drivers. The DDRAM rows to

visualized can be selected in the 0-Y-Carriage*8 range using the scrolling function.

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