SPHE8200A Просмотр технического описания (PDF) - Unspecified

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SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

0xbffe804c sft_cfg2

Description

Pin MUX control register #2 (General)

Attribute: RW

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

l Y Bit-field SWAP BRS BRP BRE

TV_LCD

UART1

UART0

IOP

tia Reset

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

n OG ATAPI

fide OL C IOP

Con CHN E IN UART0

SunUplNusNIRCCTHEAENDOINSLY UART1

For S& ME US TV_LCD

ATAPI interface

0: Disable (default)

1: Enabled

IOP reset system

0: Disable (default)

1: Enabled

UART0 select

000: Disabled

001: UA0_RX is from pin 19, UA0_TXD is from pin 20

010: UA0_RX is from pin 65, UA0_TXD is from pin 66

011: UA0_RX is from pin 130, UA0_TXD is from pin 131

100: UA0_RX is from pin 144, UA0_TXD is from pin 145

101: UA0_RX is from pin 175, UA0_TXD is from pin 176 (default)

011,111: available only at 256 pin package

UART1 function selection

0000: Disable (default)

0001-1111: Please refer to pin-description

TV LCD function selection

000: Disable (default)

0

ATAPI

0

001-111: please refer to pin-description

BRE

Bootstrap enable bit

0: Disable (default)

1: Enable

BRP

Bootstrap RXD pull up enable (pin 175)

0: Internal pull up disable (default)

1: Internal pull up enable

BRS

Bootstrap UART select

0: Bootstrap from UART0 (default)

1: Bootstrap from UART1

SWAP

SWAP UART0 and UART1

0: No swap (default)

© Sunplus Technology Co., Ltd.

33

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

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