SII161A Просмотр технического описания (PDF) - Unspecified
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SII161A Datasheet PDF : 22 Pages
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Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
AC Specifications (continued)
Under normal operating conditions unless otherwise specified.
Symbol Parameter
Conditions Min Typ Max Units
RCIP
ODCK Cycle Time1
(1-pixel/clock)
FCIP
ODCK Frequency1
(1-pixel/clock)
RCIP
ODCK Cycle Time1
(2-pixels/clock)
FCIP
ODCK Frequency1
(2-pixels/clock)
RCIH
ODCK High Time4
(165MHz, 1-pixel/clock, PIXS = 0)
CL = 10pF;
ST = 1
6.06
25
12.1
12.5
1.7
40
165
80
82.5
ns
MHz
ns
MHz
ns
RCIL
ODCK Low Time4
(165MHz, 1-pixel/clock, PIXS = 0)
CL = 5pF;
1.3
ns
ST = 0
CL = 10pF;
2.0
ns
ST = 1
CL = 5pF;
1.4
ns
ST = 0
TPDL
Delay from PD Low to high impedance outputs1
THSC
Link disabled (DE inactive) to SCDT low1
Link disabled (Tx power down) to SCDT low5
10
ns
100
ms
250
ms
TFSC
Link enabled (DE active) to SCDT high1
25 40
DE
edges
TST
Notes:
ODCK high to even data output1
0.25
RCIP
1 Guaranteed by design.
2 Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3 Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
4 Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5 Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4).
Setup and Hold Timings for data rates other than 165 MHz:
The measurements shown above are minimum setup and hold timings based on the maximum data rate of 165 MHz.
To estimate the setup and hold times for slower data rates (for either different resolutions or 2 pixel per clock mode),
the following formula can be used:
Time (at new frequency) = Time (165 MHz) + (Clock Period at new frequency – Clock Period at 165 MHz)/2
For the case of high strength output (ST=1) with a 10 pf load, and using the standard ODCK (ODCK_INV = 0), the
table below shows the minimum set up and hold times for other speeds as follows:
Data Rate (MHz)
165
112
82.5
56
Clock (ns) Setup (ns) Hold (ns)
6.06
0.70
3.80 UXGA 1 pixel/clock
8.93
2.13
5.23 SXGA 1 pixel/clock
12.12
3.73
6.83 UXGA 2 pixels/clock
17.86
6.60
9.70 SXGA 2 pixels/clock
Silicon Image, Inc.
6
Subject to Change without Notice
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