SII161A Просмотр технического описания (PDF) - Unspecified
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SII161A Datasheet PDF : 22 Pages
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Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter
Conditions Min Typ Max Units
TDPS
Intra-Pair (+ to -) Differential Input Skew1
TCCS
Channel to Channel Differential Input Skew1
165MHz
165MHz
245
ps
4
ns
TIJIT
Worst Case Differential Input Clock Jitter
tolerance2,3
65 MHz
112 MHz
465
ps
270
ps
165 MHz
182
ps
DLHT
Low-to-High Transition Time: Data and Controls
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
2.6
ns
CL = 5pF;
ST = 0
2.7
ns
Low-to-High Transition Time: Data and Controls
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
2.4
ns
CL = 5pF;
ST = 0
3.0
ns
Low-to-High Transition Time: ODCK
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
1.3
ns
CL = 5pF;
ST = 0
1.7
ns
Low-to-High Transition Time: ODCK
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
1.4
ns
CL = 5pF;
ST = 0
1.7
ns
DHLT
High-to-Low Transition Time: Data and Controls
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
2.8
ns
CL = 5pF;
ST = 0
3.4
ns
High-to-Low Transition Time: Data and Controls
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
2.3
ns
CL = 5pF;
ST = 0
3.3
ns
High-to-Low Transition Time: ODCK
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
1.1
ns
CL = 5pF;
ST = 0
1.5
ns
High-to-Low Transition Time: ODCK
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
1.2
ns
CL = 5pF;
ST = 0
1.5
ns
TSETUP
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup
CL = 10pF;
0.7
ns
Time to ODCK falling edge (OCK_INV = 0) or to
ST = 1
*0.7
ODCK rising edge (OCK_INV = 1) at 165 MHz
*OCK_INV = 1
CL = 5pF;
0.7
ns
ST = 0
*0.4
THOLD
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time CL = 10pF;
3.8
ns
from ODCK falling edge, (OCK_INV = 0) or from
ST = 1
*3.8
ODCK rising edge (OCK_INV = 1) at 165 MHz,
*OCK_INV = 0
CL = 5pF;
4.2
ns
ST = 0
*3.8
Notes:
1 Guaranteed by design.
2 Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3 Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
4 Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5 Measured when transmitter was powered down (see SiI /AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4).
Silicon Image, Inc.
5
Subject to Change without Notice
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