SII161A Просмотр технического описания (PDF) - Unspecified

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SII161A

PanelLink® Receiver

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Silicon Image, Inc.

SiI 161A

SiI-DS-0009-D

TFT Panel Data Mapping

The following table shows the output data mapping in one pixel per clock mode for the SiI 161A. This output data

mapping is dependent upon the SiI PanelLink transmitters having the exact same type of input data mappings.

Please refer to the SiI PanelLink transmitter for the specific input data mappings and to the TFT Signal Mapping

application note (SiI AN-0007).

SiI 161A

1-Pixel/Clock Output

18bpp

24bpp

BLUE[7:0]

QE[7:2]

QE[7:0]

GREEN[7:0] QE[15:10] QE[15:8]

RED[7:0]

QE[23:18] QE[23:16]

Table 1. One Pixel/Clock Mode Data Mapping

BLUE[7:0] - 0

GREEN[7:0] – 0

RED[7:0] – 0

BLUE[7:0] – 1

GREEN[7:0] – 1

RED[7:0] – 1

SiI 161A

2-Pixel/Clock Output

18bpp

24bpp

QE[7:2]

QE[7:0]

QE[15:10] QE[15:8]

QE[23:18] QE[23:16]

QO[7:2] QO[7:0]

QO[15:10] QO[15:8]

QO[23:18] QO[23:16]

Table 2. Two Pixel/Clock Mode Data Mapping

Note: For 18-bit mode, the Flat Panel Timing Controller interfaces to the SiI 161A exactly the same as in the 24-bit

mode; however, only 6-bits per channel (color) are interfaced instead of the full 8. As can be seen from the above

table, the data mapping for less than 24-bit per pixel interfaces are MSB justified.

Silicon Image, Inc.

13

Subject to Change without Notice

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