S3C7324 Просмотр технического описания (PDF) - Samsung

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S3C7324

The S3C7335 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47

Samsung 

PRODUCT OVERVIEW

S3C7324/P7324

Table 1-1. S3P7324 Pin Descriptions (Continued)

Pin Name

SEG20–SEG27

ADC0–ADC3

FMF

AMF

INT4

INT2

INT1

INT0

BUZ

KS0–KS2

RESET

TEST

Pin

Type

Description

Number

Share

Pin

Reset Circuit

Value Type

O LCD segment signal output

40–33 P9.0–P9.3 Output H-16

P8.0–P8.3

I ADC input ports

5–8 P3.0–P3.3 Input F-13

I External FM/AM frequency inputs

3

P2.2

Input B-4

4

P2.3

I External interrupt input with detection of

20

rising or falling edges.

P1.3

Input A-4

I Quasi-interrupt with detection of rising

19

edge signals.

P1.2

Input A-4

I External interrupt. The triggering edges

18

for INT0 and INT1 are able to be

17

selected. Only INT0 is synchronized with

the system clock.

P1.1

P1.0

Input A-4

O 2, 4, 8, or 16 kHz frequency output for

29

buzzer sound with 4.19 MHz main

system clock.

P6.0

Input D-2

I Quasi-interrupt input with falling edge

detection.

30–32 P6.1–P6.3 Input D-4

I System reset signal

16

–

Input

B

– System test pin(must be connected to

13

–

–

–

VSS)

NOTE: Pull-up resistors forall I/O ports automatically disabled if they are configured to output mode.

1-6

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