CY7C1314V18-167BZC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1314V18-167BZC Datasheet PDF : 25 Pages
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PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Pin Definitions (continued)
Pin Name
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
VSS/72M
VSS/144M
VSS/288M
VREF
VDD
VSS
VDDQ
I/O
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input-
Reference
Power Supply
Ground
Power Supply
Pin Description
Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ
is a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to VDD, which enables the minimum impedance mode. This pin cannot be
connected directly to GND or left unconnected.
DLL Turn Off. Connecting this pin to ground will turn off the DLL inside the device. The
timings in the DLL turned off operation will be different from those listed in this data
sheet. More details on this operation can be found in the application note, “DLL
Operation in the QDRTM-II.”
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
No connects inside the package. Can be tied to any voltage level.
Address expansion for 36M. This is not connected to the die and so can be tied to any
voltage level.
Address expansion for 72M. This is not connected to the die and so can be tied to any
voltage level.
Address expansion for 72M. This must be tied LOW on the 18M devices.
Address expansion for 144M. This must be tied LOW on the 18M devices.
Address expansion for 288M. This must be tied LOW on the 18M devices.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device. Should be connected to 1.8V power
supply.
Ground for the device. Should be connected to ground of the system.
Power supply inputs for the outputs of the device. Should be connected to 1.5V
power supply.
Introduction
Functional Overview
The CY7C1310V18/CY7C1312V18/CY7C1314V18 are
synchronous pipelined Burst SRAMs equipped with both a
Read port and a Write port. The Read port is dedicated to
Read operations and the Write port is dedicated to Write
operations. Data flows into the SRAM through the Write port
and out through the Read Port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write ports, the
QDRTM-II completely eliminates the need to “turn-around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 8-bit
data transfers in the case of CY7C1310V18, two 18-bit data
transfers in the case of CY7C1312V18 and two 36-bit data
transfers in the case of CY7C1314V18, in one clock cycles.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the output clocks (C
and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
The following descriptions take CY7C1312V18 as an
example. However, the same is true for the other QDRTM-II
SRAMs, CY7C1310V18 and CY7C1314V18.
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin.
Read Operations
The CY7C1312V18 is organized internally as a 512Kx36
SRAM. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corre-
sponding lowest order 18-bit word of data is driven onto the
Q[17:0] using C as the output timing reference. On the subse-
quent rising edge of C, the next 18-bit data word is driven onto
Document #: 38-05180 Rev. *A
Page 6 of 25
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