PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
Logic Block Diagram (CY7C1312V18)
D[17:0] 18
A(18:0)
19
Address
Register
K
K
CLK
Gen.
VREF
WPS
BWS[1:0]
Control
Logic
Logic Block Diagram (CY7C1314V18)
D[35:0] 36
A(17:0)
18
K
K
Address
Register
CLK
Gen.
VREF
WPS
BWS[3:0]
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
36 18
18
Write
Reg
Write
Reg
Read Data Reg.
72 36
36
Address
Register
19 A(18:0)
Control
Logic
Reg.
Reg.
Reg. 18
18
RPS
C
C
CQ
CQ
18
Q[17:0]
Address
Register
18 A(17:0)
Control
Logic
RPS
C
C
CQ
CQ
Reg.
Reg. 36
Reg.
36
36 Q[35:0]
Selection Guide[1]
Maximum Operating Frequency
Maximum Operating Current
Note:
1. Shaded cells indicate advanced information.
200 MHz
200
TBD
167 MHz
167
TBD
133 MHz
133
TBD
Unit
MHz
mA
Document #: 38-05180 Rev. *A
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